0037-ar71xx-update-QCA956x-support.patch 11 KB

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  1. From: Matthias Schiffer <mschiffer@universe-factory.net>
  2. Date: Fri, 13 May 2016 22:18:40 +0200
  3. Subject: ar71xx: update QCA956x support
  4. - separate qca956x and tp9343 (they use different IDs)
  5. - rename qca9561->qca956x for consistency
  6. - add missing bits (device reset, gpio output select)
  7. - fix wmac setup
  8. Signed-off-by: Roman Yeryomin <roman@advem.lv>
  9. Backport of OpenWrt r47981
  10. diff --git a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
  11. index d3a14b2..61b8976 100644
  12. --- a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
  13. +++ b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
  14. @@ -105,7 +105,7 @@
  15. qca953x_clocks_init();
  16. else if (soc_is_qca955x())
  17. qca955x_clocks_init();
  18. -+ else if (soc_is_qca956x())
  19. ++ else if (soc_is_qca956x() || soc_is_tp9343())
  20. + qca956x_clocks_init();
  21. else
  22. BUG();
  23. @@ -116,7 +116,7 @@
  24. reg = QCA953X_RESET_REG_RESET_MODULE;
  25. else if (soc_is_qca955x())
  26. reg = QCA955X_RESET_REG_RESET_MODULE;
  27. -+ else if (soc_is_qca956x())
  28. ++ else if (soc_is_qca956x() || soc_is_tp9343())
  29. + reg = QCA956X_RESET_REG_RESET_MODULE;
  30. else
  31. panic("Reset register not defined for this SOC");
  32. @@ -125,20 +125,30 @@
  33. reg = QCA953X_RESET_REG_RESET_MODULE;
  34. else if (soc_is_qca955x())
  35. reg = QCA955X_RESET_REG_RESET_MODULE;
  36. -+ else if (soc_is_qca956x())
  37. ++ else if (soc_is_qca956x() || soc_is_tp9343())
  38. + reg = QCA956X_RESET_REG_RESET_MODULE;
  39. else
  40. panic("Reset register not defined for this SOC");
  41. +@@ -133,6 +137,8 @@ u32 ath79_device_reset_get(u32 mask)
  42. + reg = AR933X_RESET_REG_RESET_MODULE;
  43. + else if (soc_is_ar934x())
  44. + reg = AR934X_RESET_REG_RESET_MODULE;
  45. ++ else if (soc_is_qca956x() || soc_is_tp9343())
  46. ++ reg = QCA956X_RESET_REG_RESET_MODULE;
  47. + else
  48. + BUG();
  49. +
  50. --- a/arch/mips/ath79/dev-common.c
  51. +++ b/arch/mips/ath79/dev-common.c
  52. -@@ -94,7 +94,8 @@ void __init ath79_register_uart(void)
  53. +@@ -94,7 +94,9 @@ void __init ath79_register_uart(void)
  54. soc_is_ar913x() ||
  55. soc_is_ar934x() ||
  56. soc_is_qca953x() ||
  57. - soc_is_qca955x()) {
  58. + soc_is_qca955x() ||
  59. -+ soc_is_qca956x()) {
  60. ++ soc_is_qca956x() ||
  61. ++ soc_is_tp9343()) {
  62. ath79_uart_data[0].uartclk = uart_clk_rate;
  63. platform_device_register(&ath79_uart_device);
  64. } else if (soc_is_ar933x()) {
  65. @@ -168,14 +178,14 @@
  66. qca953x_usb_setup();
  67. else if (soc_is_qca955x())
  68. qca955x_usb_setup();
  69. -+ else if (soc_is_qca9561())
  70. ++ else if (soc_is_qca956x())
  71. + qca956x_usb_setup();
  72. else
  73. BUG();
  74. }
  75. --- a/arch/mips/ath79/dev-wmac.c
  76. +++ b/arch/mips/ath79/dev-wmac.c
  77. -@@ -189,6 +189,24 @@ static void qca955x_wmac_setup(void)
  78. +@@ -189,6 +189,26 @@ static void qca955x_wmac_setup(void)
  79. ath79_wmac_data.is_clk_25mhz = true;
  80. }
  81. @@ -195,16 +205,18 @@
  82. + ath79_wmac_data.is_clk_25mhz = false;
  83. + else
  84. + ath79_wmac_data.is_clk_25mhz = true;
  85. ++
  86. ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
  87. +}
  88. +
  89. static bool __init
  90. ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
  91. {
  92. -@@ -392,6 +410,8 @@ void __init ath79_register_wmac(u8 *cal_
  93. +@@ -392,6 +412,8 @@ void __init ath79_register_wmac(u8 *cal_
  94. qca953x_wmac_setup();
  95. else if (soc_is_qca955x())
  96. qca955x_wmac_setup();
  97. -+ else if (soc_is_qca956x())
  98. ++ else if (soc_is_qca956x() || soc_is_tp9343())
  99. + qca956x_wmac_setup();
  100. else
  101. BUG();
  102. @@ -216,27 +228,38 @@
  103. case REV_ID_MAJOR_QCA9556:
  104. case REV_ID_MAJOR_QCA9558:
  105. + case REV_ID_MAJOR_TP9343:
  106. -+ case REV_ID_MAJOR_QCA9561:
  107. ++ case REV_ID_MAJOR_QCA956X:
  108. _prom_putchar = prom_putchar_ar71xx;
  109. break;
  110. --- a/arch/mips/ath79/gpio.c
  111. +++ b/arch/mips/ath79/gpio.c
  112. -@@ -148,7 +148,8 @@ static void __iomem *ath79_gpio_get_func
  113. +@@ -148,7 +148,10 @@ static void __iomem *ath79_gpio_get_func
  114. soc_is_ar913x() ||
  115. soc_is_ar933x())
  116. reg = AR71XX_GPIO_REG_FUNC;
  117. - else if (soc_is_ar934x() || soc_is_qca953x())
  118. + else if (soc_is_ar934x() ||
  119. -+ soc_is_qca953x() || soc_is_qca956x())
  120. ++ soc_is_qca953x() ||
  121. ++ soc_is_qca956x() ||
  122. ++ soc_is_tp9343())
  123. reg = AR934X_GPIO_REG_FUNC;
  124. else
  125. BUG();
  126. -@@ -228,12 +229,15 @@ void __init ath79_gpio_init(void)
  127. +@@ -187,7 +190,7 @@ void __init ath79_gpio_output_select(uns
  128. + unsigned int reg;
  129. + u32 t, s;
  130. +
  131. +- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
  132. ++ BUG_ON(!soc_is_ar934x() && !soc_is_qca953x() && !soc_is_qca956x());
  133. +
  134. + if (gpio >= AR934X_GPIO_COUNT)
  135. + return;
  136. +@@ -228,12 +231,15 @@ void __init ath79_gpio_init(void)
  137. ath79_gpio_count = QCA953X_GPIO_COUNT;
  138. else if (soc_is_qca955x())
  139. ath79_gpio_count = QCA955X_GPIO_COUNT;
  140. -+ else if (soc_is_qca956x())
  141. ++ else if (soc_is_qca956x() || soc_is_tp9343())
  142. + ath79_gpio_count = QCA956X_GPIO_COUNT;
  143. else
  144. BUG();
  145. @@ -245,23 +268,24 @@
  146. ath79_gpio_chip.ngpio = ath79_gpio_count;
  147. - if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
  148. + if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() ||
  149. -+ soc_is_qca956x()) {
  150. ++ soc_is_qca956x() || soc_is_tp9343()) {
  151. ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
  152. ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
  153. }
  154. --- a/arch/mips/ath79/irq.c
  155. +++ b/arch/mips/ath79/irq.c
  156. -@@ -107,7 +107,8 @@ static void __init ath79_misc_irq_init(v
  157. +@@ -107,7 +107,9 @@ static void __init ath79_misc_irq_init(v
  158. soc_is_ar933x() ||
  159. soc_is_ar934x() ||
  160. soc_is_qca953x() ||
  161. - soc_is_qca955x())
  162. + soc_is_qca955x() ||
  163. -+ soc_is_qca956x())
  164. ++ soc_is_qca956x() ||
  165. ++ soc_is_tp9343())
  166. ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
  167. else
  168. BUG();
  169. -@@ -268,6 +269,97 @@ static void qca955x_irq_init(void)
  170. +@@ -268,6 +270,97 @@ static void qca955x_irq_init(void)
  171. irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
  172. }
  173. @@ -359,21 +383,21 @@
  174. asmlinkage void plat_irq_dispatch(void)
  175. {
  176. unsigned long pending;
  177. -@@ -397,6 +489,9 @@ void __init arch_init_irq(void)
  178. +@@ -397,6 +490,9 @@ void __init arch_init_irq(void)
  179. } else if (soc_is_qca955x()) {
  180. ath79_ip2_handler = ath79_default_ip2_handler;
  181. ath79_ip3_handler = ath79_default_ip3_handler;
  182. -+ } else if (soc_is_qca956x()) {
  183. ++ } else if (soc_is_qca956x() || soc_is_tp9343()) {
  184. + ath79_ip2_handler = ath79_default_ip2_handler;
  185. + ath79_ip3_handler = ath79_default_ip3_handler;
  186. } else {
  187. BUG();
  188. }
  189. -@@ -411,4 +506,6 @@ void __init arch_init_irq(void)
  190. +@@ -411,4 +507,6 @@ void __init arch_init_irq(void)
  191. qca953x_irq_init();
  192. else if (soc_is_qca955x())
  193. qca955x_irq_init();
  194. -+ else if (soc_is_qca956x())
  195. ++ else if (soc_is_qca956x() || soc_is_tp9343())
  196. + qca956x_irq_init();
  197. }
  198. --- a/arch/mips/ath79/Kconfig
  199. @@ -428,7 +452,7 @@
  200. } else if (soc_is_qca955x()) {
  201. ath79_pci_irq_map = qca955x_pci_irq_map;
  202. ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
  203. -+ } else if (soc_is_qca9561()) {
  204. ++ } else if (soc_is_qca956x()) {
  205. + ath79_pci_irq_map = qca956x_pci_irq_map;
  206. + ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
  207. } else {
  208. @@ -438,7 +462,7 @@
  209. QCA955X_PCI_MEM_SIZE,
  210. 1,
  211. ATH79_IP3_IRQ(2));
  212. -+ } else if (soc_is_qca9561()) {
  213. ++ } else if (soc_is_qca956x()) {
  214. + pdev = ath79_register_pci_ar724x(0,
  215. + QCA956X_PCI_CFG_BASE1,
  216. + QCA956X_PCI_CTRL_BASE1,
  217. @@ -456,15 +480,15 @@
  218. rev = id & QCA955X_REV_ID_REVISION_MASK;
  219. break;
  220. -+ case REV_ID_MAJOR_TP9343:
  221. -+ ath79_soc = ATH79_SOC_TP9343;
  222. -+ chip = "9343";
  223. ++ case REV_ID_MAJOR_QCA956X:
  224. ++ ath79_soc = ATH79_SOC_QCA956X;
  225. ++ chip = "956X";
  226. + rev = id & QCA956X_REV_ID_REVISION_MASK;
  227. + break;
  228. +
  229. -+ case REV_ID_MAJOR_QCA9561:
  230. -+ ath79_soc = ATH79_SOC_QCA9561;
  231. -+ chip = "9561";
  232. ++ case REV_ID_MAJOR_TP9343:
  233. ++ ath79_soc = ATH79_SOC_TP9343;
  234. ++ chip = "9343";
  235. + rev = id & QCA956X_REV_ID_REVISION_MASK;
  236. + break;
  237. +
  238. @@ -476,7 +500,7 @@
  239. ath79_soc_rev = rev;
  240. - if (soc_is_qca953x() || soc_is_qca955x())
  241. -+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
  242. ++ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
  243. sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
  244. chip, ver, rev);
  245. + else if (soc_is_tp9343())
  246. @@ -511,7 +535,21 @@
  247. #define AR9300_OTP_BASE 0x14000
  248. #define AR9300_OTP_STATUS 0x15f18
  249. #define AR9300_OTP_STATUS_TYPE 0x7
  250. -@@ -375,6 +392,49 @@
  251. +@@ -152,6 +169,13 @@
  252. + #define AR9300_OTP_READ_DATA 0x15f1c
  253. +
  254. + /*
  255. ++ * Hidden Registers
  256. ++ */
  257. ++#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
  258. ++#define QCA956X_DAM_RESET_SIZE 0x4
  259. ++#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
  260. ++
  261. ++/*
  262. + * DDR_CTRL block
  263. + */
  264. + #define AR71XX_DDR_REG_PCI_WIN0 0x7c
  265. +@@ -375,6 +399,49 @@
  266. #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
  267. #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  268. @@ -561,7 +599,7 @@
  269. /*
  270. * USB_CONFIG block
  271. */
  272. -@@ -422,6 +482,11 @@
  273. +@@ -422,6 +489,11 @@
  274. #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
  275. #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
  276. @@ -573,7 +611,7 @@
  277. #define MISC_INT_ETHSW BIT(12)
  278. #define MISC_INT_TIMER4 BIT(10)
  279. #define MISC_INT_TIMER3 BIT(9)
  280. -@@ -596,6 +661,8 @@
  281. +@@ -596,6 +668,8 @@
  282. #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
  283. @@ -582,7 +620,7 @@
  284. #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
  285. #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
  286. #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
  287. -@@ -663,6 +730,37 @@
  288. +@@ -663,6 +737,37 @@
  289. QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
  290. QCA955X_EXT_INT_PCIE_RC2_INT3)
  291. @@ -620,16 +658,16 @@
  292. #define REV_ID_MAJOR_MASK 0xfff0
  293. #define REV_ID_MAJOR_AR71XX 0x00a0
  294. #define REV_ID_MAJOR_AR913X 0x00b0
  295. -@@ -678,6 +776,8 @@
  296. +@@ -678,6 +783,8 @@
  297. #define REV_ID_MAJOR_QCA9533_V2 0x0160
  298. #define REV_ID_MAJOR_QCA9556 0x0130
  299. #define REV_ID_MAJOR_QCA9558 0x1130
  300. +#define REV_ID_MAJOR_TP9343 0x0150
  301. -+#define REV_ID_MAJOR_QCA9561 0x1150
  302. ++#define REV_ID_MAJOR_QCA956X 0x1150
  303. #define AR71XX_REV_ID_MINOR_MASK 0x3
  304. #define AR71XX_REV_ID_MINOR_AR7130 0x0
  305. -@@ -702,6 +802,8 @@
  306. +@@ -702,6 +809,8 @@
  307. #define QCA955X_REV_ID_REVISION_MASK 0xf
  308. @@ -638,7 +676,7 @@
  309. /*
  310. * SPI block
  311. */
  312. -@@ -766,6 +868,19 @@
  313. +@@ -766,6 +875,19 @@
  314. #define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
  315. #define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
  316. @@ -658,7 +696,7 @@
  317. #define AR71XX_GPIO_COUNT 16
  318. #define AR7240_GPIO_COUNT 18
  319. #define AR7241_GPIO_COUNT 20
  320. -@@ -774,6 +889,7 @@
  321. +@@ -774,6 +896,7 @@
  322. #define AR934X_GPIO_COUNT 23
  323. #define QCA953X_GPIO_COUNT 18
  324. #define QCA955X_GPIO_COUNT 24
  325. @@ -673,11 +711,11 @@
  326. ATH79_SOC_QCA9556,
  327. ATH79_SOC_QCA9558,
  328. + ATH79_SOC_TP9343,
  329. -+ ATH79_SOC_QCA9561,
  330. ++ ATH79_SOC_QCA956X,
  331. };
  332. extern enum ath79_soc_type ath79_soc;
  333. -@@ -126,6 +128,21 @@ static inline int soc_is_qca955x(void)
  334. +@@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
  335. return soc_is_qca9556() || soc_is_qca9558();
  336. }
  337. @@ -685,15 +723,20 @@
  338. +{
  339. + return ath79_soc == ATH79_SOC_TP9343;
  340. +}
  341. -+
  342. ++
  343. +static inline int soc_is_qca9561(void)
  344. +{
  345. -+ return ath79_soc == ATH79_SOC_QCA9561;
  346. ++ return ath79_soc == ATH79_SOC_QCA956X;
  347. ++}
  348. ++
  349. ++static inline int soc_is_qca9563(void)
  350. ++{
  351. ++ return ath79_soc == ATH79_SOC_QCA956X;
  352. +}
  353. +
  354. +static inline int soc_is_qca956x(void)
  355. +{
  356. -+ return soc_is_tp9343() || soc_is_qca9561();
  357. ++ return soc_is_qca9561() || soc_is_qca9563();
  358. +}
  359. +
  360. extern void __iomem *ath79_ddr_base;