0036-ar71xx-use-correct-PLL-configuration-register-bitmask-for-QCA956x-SoC.patch 1.5 KB

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  1. From: Matthias Schiffer <mschiffer@universe-factory.net>
  2. Date: Fri, 13 May 2016 22:58:50 +0200
  3. Subject: ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
  4. Incorrect value causes clock inaccuracy as huge as 1/60.
  5. Signed-off-by: Dmitry Ivanov <dima@ubnt.com>
  6. Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  7. Backport of OpenWrt r47363
  8. diff --git a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
  9. index b5c88e9..d3a14b2 100644
  10. --- a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
  11. +++ b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
  12. @@ -529,7 +529,7 @@
  13. +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
  14. +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
  15. +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
  16. -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff
  17. ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
  18. +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
  19. +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
  20. +
  21. @@ -541,7 +541,7 @@
  22. +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
  23. +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
  24. +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
  25. -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff
  26. ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
  27. +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
  28. +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
  29. +