0035-ar71xx-fold-patch-622-MIPS-ath79-add-support-for-QCA956x-ethernet.patch-into-files.patch 4.9 KB

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  1. From: Matthias Schiffer <mschiffer@universe-factory.net>
  2. Date: Fri, 13 May 2016 21:00:16 +0200
  3. Subject: ar71xx: fold patch 622-MIPS-ath79-add-support-for-QCA956x-ethernet.patch into files/
  4. Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  5. Backport of OpenWrt r48650
  6. diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  7. index 31d2438..2efb9c7 100644
  8. --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  9. +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  10. @@ -198,7 +198,6 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
  11. case ATH79_SOC_AR9330:
  12. case ATH79_SOC_AR9331:
  13. case ATH79_SOC_QCA9533:
  14. - case ATH79_SOC_QCA9561:
  15. case ATH79_SOC_TP9343:
  16. mdio_dev = &ath79_mdio1_device;
  17. mdio_data = &ath79_mdio1_data;
  18. @@ -209,6 +208,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
  19. case ATH79_SOC_AR9344:
  20. case ATH79_SOC_QCA9556:
  21. case ATH79_SOC_QCA9558:
  22. + case ATH79_SOC_QCA956X:
  23. if (id == 0) {
  24. mdio_dev = &ath79_mdio0_device;
  25. mdio_data = &ath79_mdio0_data;
  26. @@ -258,7 +258,6 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
  27. break;
  28. case ATH79_SOC_QCA9533:
  29. - case ATH79_SOC_QCA9561:
  30. case ATH79_SOC_TP9343:
  31. mdio_data->builtin_switch = 1;
  32. break;
  33. @@ -268,6 +267,11 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
  34. mdio_data->is_ar934x = 1;
  35. break;
  36. + case ATH79_SOC_QCA956X:
  37. + if (id == 1)
  38. + mdio_data->builtin_switch = 1;
  39. + break;
  40. +
  41. default:
  42. break;
  43. }
  44. @@ -387,6 +391,16 @@ static void qca955x_set_speed_sgmii(int speed)
  45. iounmap(base);
  46. }
  47. +static void qca956x_set_speed_sgmii(int speed)
  48. +{
  49. + void __iomem *base;
  50. + u32 val = ath79_get_eth_pll(0, speed);
  51. +
  52. + base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  53. + __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
  54. + iounmap(base);
  55. +}
  56. +
  57. static void ath79_set_speed_dummy(int speed)
  58. {
  59. }
  60. @@ -517,6 +531,10 @@ struct ag71xx_switch_platform_data ath79_switch_data;
  61. #define AR934X_PLL_VAL_100 0x00000101
  62. #define AR934X_PLL_VAL_10 0x00001616
  63. +#define QCA956X_PLL_VAL_1000 0x03000000
  64. +#define QCA956X_PLL_VAL_100 0x00000101
  65. +#define QCA956X_PLL_VAL_10 0x00001919
  66. +
  67. static void __init ath79_init_eth_pll_data(unsigned int id)
  68. {
  69. struct ath79_eth_pll_data *pll_data;
  70. @@ -575,13 +593,18 @@ static void __init ath79_init_eth_pll_data(unsigned int id)
  71. case ATH79_SOC_QCA9533:
  72. case ATH79_SOC_QCA9556:
  73. case ATH79_SOC_QCA9558:
  74. - case ATH79_SOC_QCA9561:
  75. case ATH79_SOC_TP9343:
  76. pll_10 = AR934X_PLL_VAL_10;
  77. pll_100 = AR934X_PLL_VAL_100;
  78. pll_1000 = AR934X_PLL_VAL_1000;
  79. break;
  80. + case ATH79_SOC_QCA956X:
  81. + pll_10 = QCA956X_PLL_VAL_10;
  82. + pll_100 = QCA956X_PLL_VAL_100;
  83. + pll_1000 = QCA956X_PLL_VAL_1000;
  84. + break;
  85. +
  86. default:
  87. BUG();
  88. }
  89. @@ -656,6 +679,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
  90. case ATH79_SOC_QCA9556:
  91. case ATH79_SOC_QCA9558:
  92. + case ATH79_SOC_QCA956X:
  93. switch (pdata->phy_if_mode) {
  94. case PHY_INTERFACE_MODE_MII:
  95. case PHY_INTERFACE_MODE_RGMII:
  96. @@ -666,11 +690,6 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
  97. }
  98. break;
  99. - case ATH79_SOC_QCA9561:
  100. - if (!pdata->phy_if_mode)
  101. - pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
  102. - break;
  103. -
  104. default:
  105. BUG();
  106. }
  107. @@ -699,7 +718,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
  108. case ATH79_SOC_AR7241:
  109. case ATH79_SOC_AR9330:
  110. case ATH79_SOC_AR9331:
  111. - case ATH79_SOC_QCA9561:
  112. + case ATH79_SOC_QCA956X:
  113. case ATH79_SOC_TP9343:
  114. pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
  115. break;
  116. @@ -1032,7 +1051,6 @@ void __init ath79_register_eth(unsigned int id)
  117. pdata->fifo_cfg3 = 0x01f00140;
  118. break;
  119. - case ATH79_SOC_QCA9561:
  120. case ATH79_SOC_TP9343:
  121. if (id == 0) {
  122. pdata->reset_bit = AR933X_RESET_GE0_MAC |
  123. @@ -1100,6 +1118,34 @@ void __init ath79_register_eth(unsigned int id)
  124. pdata->fifo_cfg3 = 0x01f00140;
  125. break;
  126. + case ATH79_SOC_QCA956X:
  127. + if (id == 0) {
  128. + pdata->reset_bit = QCA955X_RESET_GE0_MAC |
  129. + QCA955X_RESET_GE0_MDIO;
  130. + if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
  131. + pdata->set_speed = qca956x_set_speed_sgmii;
  132. + else
  133. + /* FIXME */
  134. + pdata->set_speed = ath79_set_speed_dummy;
  135. + } else {
  136. + pdata->reset_bit = QCA955X_RESET_GE1_MAC |
  137. + QCA955X_RESET_GE1_MDIO;
  138. + /* FIXME */
  139. + pdata->set_speed = ath79_set_speed_dummy;
  140. + }
  141. +
  142. + pdata->ddr_flush = ath79_ddr_no_flush;
  143. + pdata->has_gbit = 1;
  144. + pdata->is_ar724x = 1;
  145. +
  146. + if (!pdata->fifo_cfg1)
  147. + pdata->fifo_cfg1 = 0x0010ffff;
  148. + if (!pdata->fifo_cfg2)
  149. + pdata->fifo_cfg2 = 0x015500aa;
  150. + if (!pdata->fifo_cfg3)
  151. + pdata->fifo_cfg3 = 0x01f00140;
  152. + break;
  153. +
  154. default:
  155. BUG();
  156. }
  157. @@ -1140,7 +1186,6 @@ void __init ath79_register_eth(unsigned int id)
  158. case ATH79_SOC_AR9330:
  159. case ATH79_SOC_AR9331:
  160. case ATH79_SOC_QCA9533:
  161. - case ATH79_SOC_QCA9561:
  162. case ATH79_SOC_TP9343:
  163. pdata->mii_bus_dev = &ath79_mdio1_device.dev;
  164. break;