0026-kernel-backport-spi-nor-driver-from-4.4.9.patch 73 KB

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  1. From: Matthias Schiffer <mschiffer@universe-factory.net>
  2. Date: Sat, 7 May 2016 00:07:51 +0200
  3. Subject: kernel: backport spi-nor driver from 4.4.9
  4. diff --git a/target/linux/ar71xx/patches-3.18/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch b/target/linux/ar71xx/patches-3.18/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
  5. index 568f516..6a91320 100644
  6. --- a/target/linux/ar71xx/patches-3.18/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
  7. +++ b/target/linux/ar71xx/patches-3.18/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
  8. @@ -1,11 +1,11 @@
  9. --- a/drivers/mtd/devices/m25p80.c
  10. +++ b/drivers/mtd/devices/m25p80.c
  11. -@@ -246,7 +246,9 @@ static int m25p_probe(struct spi_device
  12. +@@ -229,7 +229,9 @@ static int m25p_probe(struct spi_device
  13. ppdata.of_node = spi->dev.of_node;
  14. -- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
  15. -+ return mtd_device_parse_register(&flash->mtd,
  16. +- return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
  17. ++ return mtd_device_parse_register(&nor->mtd,
  18. + data ? data->part_probes : NULL,
  19. + &ppdata,
  20. data ? data->parts : NULL,
  21. diff --git a/target/linux/ar71xx/patches-3.18/412-mtd-m25p80-zero-partition-parser-data.patch b/target/linux/ar71xx/patches-3.18/412-mtd-m25p80-zero-partition-parser-data.patch
  22. index d51694d..175acf6 100644
  23. --- a/target/linux/ar71xx/patches-3.18/412-mtd-m25p80-zero-partition-parser-data.patch
  24. +++ b/target/linux/ar71xx/patches-3.18/412-mtd-m25p80-zero-partition-parser-data.patch
  25. @@ -1,10 +1,10 @@
  26. --- a/drivers/mtd/devices/m25p80.c
  27. +++ b/drivers/mtd/devices/m25p80.c
  28. -@@ -244,6 +244,7 @@ static int m25p_probe(struct spi_device
  29. +@@ -227,6 +227,7 @@ static int m25p_probe(struct spi_device
  30. if (ret)
  31. return ret;
  32. + memset(&ppdata, '\0', sizeof(ppdata));
  33. ppdata.of_node = spi->dev.of_node;
  34. - return mtd_device_parse_register(&flash->mtd,
  35. + return mtd_device_parse_register(&nor->mtd,
  36. diff --git a/target/linux/ar71xx/patches-3.18/462-mtd-m25p80-set-spi-transfer-type.patch b/target/linux/ar71xx/patches-3.18/462-mtd-m25p80-set-spi-transfer-type.patch
  37. index 3320e5b..11bf9ff 100644
  38. --- a/target/linux/ar71xx/patches-3.18/462-mtd-m25p80-set-spi-transfer-type.patch
  39. +++ b/target/linux/ar71xx/patches-3.18/462-mtd-m25p80-set-spi-transfer-type.patch
  40. @@ -1,6 +1,6 @@
  41. --- a/drivers/mtd/devices/m25p80.c
  42. +++ b/drivers/mtd/devices/m25p80.c
  43. -@@ -142,10 +142,12 @@ static int m25p80_read(struct spi_nor *n
  44. +@@ -137,10 +137,12 @@ static int m25p80_read(struct spi_nor *n
  45. flash->command[0] = nor->read_opcode;
  46. m25p_addr2cmd(nor, from, flash->command);
  47. diff --git a/target/linux/ar71xx/patches-3.18/464-spi-ath79-fix-fast-flash-read.patch b/target/linux/ar71xx/patches-3.18/464-spi-ath79-fix-fast-flash-read.patch
  48. index e48665d..758d231 100644
  49. --- a/target/linux/ar71xx/patches-3.18/464-spi-ath79-fix-fast-flash-read.patch
  50. +++ b/target/linux/ar71xx/patches-3.18/464-spi-ath79-fix-fast-flash-read.patch
  51. @@ -1,6 +1,6 @@
  52. --- a/drivers/mtd/devices/m25p80.c
  53. +++ b/drivers/mtd/devices/m25p80.c
  54. -@@ -142,6 +142,9 @@ static int m25p80_read(struct spi_nor *n
  55. +@@ -137,6 +137,9 @@ static int m25p80_read(struct spi_nor *n
  56. flash->command[0] = nor->read_opcode;
  57. m25p_addr2cmd(nor, from, flash->command);
  58. @@ -25,7 +25,7 @@
  59. while (len--) {
  60. --- a/include/linux/spi/spi.h
  61. +++ b/include/linux/spi/spi.h
  62. -@@ -637,6 +637,7 @@ struct spi_transfer {
  63. +@@ -633,6 +633,7 @@ struct spi_transfer {
  64. u16 delay_usecs;
  65. u32 speed_hz;
  66. enum spi_transfer_type type;
  67. diff --git a/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch b/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch
  68. index b949694..be62e67 100644
  69. --- a/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch
  70. +++ b/target/linux/brcm63xx/patches-3.18/202-MTD-DEVICES-m25p80-use-parsers-if-provided-in-flash-.patch
  71. @@ -11,12 +11,12 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  72. --- a/drivers/mtd/devices/m25p80.c
  73. +++ b/drivers/mtd/devices/m25p80.c
  74. -@@ -246,7 +246,8 @@ static int m25p_probe(struct spi_device
  75. +@@ -229,7 +229,8 @@ static int m25p_probe(struct spi_device
  76. ppdata.of_node = spi->dev.of_node;
  77. -- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
  78. -+ return mtd_device_parse_register(&flash->mtd,
  79. +- return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
  80. ++ return mtd_device_parse_register(&nor->mtd,
  81. + data ? data->part_probe_types : NULL, &ppdata,
  82. data ? data->parts : NULL,
  83. data ? data->nr_parts : 0);
  84. diff --git a/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch b/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch
  85. index 740fb2d..3877442 100644
  86. --- a/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch
  87. +++ b/target/linux/brcm63xx/patches-3.18/203-MTD-DEVICES-m25p80-add-support-for-limiting-reads.patch
  88. @@ -11,15 +11,15 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  89. --- a/drivers/mtd/devices/m25p80.c
  90. +++ b/drivers/mtd/devices/m25p80.c
  91. -@@ -32,6 +32,7 @@ struct m25p {
  92. +@@ -31,6 +31,7 @@
  93. + struct m25p {
  94. struct spi_device *spi;
  95. struct spi_nor spi_nor;
  96. - struct mtd_info mtd;
  97. + int max_transfer_len;
  98. u8 command[MAX_CMD_SIZE];
  99. };
  100. -@@ -121,7 +122,7 @@ static inline unsigned int m25p80_rx_nbi
  101. +@@ -119,7 +120,7 @@ static inline unsigned int m25p80_rx_nbi
  102. * Read an address range from the nor chip. The address range
  103. * may be any size provided it is within the physical boundaries.
  104. */
  105. @@ -28,7 +28,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  106. size_t *retlen, u_char *buf)
  107. {
  108. struct m25p *flash = nor->priv;
  109. -@@ -157,6 +158,29 @@ static int m25p80_read(struct spi_nor *n
  110. +@@ -152,6 +153,29 @@ static int m25p80_read(struct spi_nor *n
  111. return 0;
  112. }
  113. @@ -58,7 +58,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
  114. static int m25p80_erase(struct spi_nor *nor, loff_t offset)
  115. {
  116. struct m25p *flash = nor->priv;
  117. -@@ -240,6 +264,9 @@ static int m25p_probe(struct spi_device
  118. +@@ -223,6 +247,9 @@ static int m25p_probe(struct spi_device
  119. else
  120. flash_name = spi->modalias;
  121. diff --git a/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch b/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch
  122. index b7bf57f..e421e9a 100644
  123. --- a/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch
  124. +++ b/target/linux/brcm63xx/patches-3.18/414-MTD-m25p80-allow-passing-pp_data.patch
  125. @@ -10,7 +10,7 @@ Subject: [PATCH 64/79] MTD: m25p80: allow passing pp_data
  126. --- a/drivers/mtd/devices/m25p80.c
  127. +++ b/drivers/mtd/devices/m25p80.c
  128. -@@ -267,6 +267,9 @@ static int m25p_probe(struct spi_device
  129. +@@ -250,6 +250,9 @@ static int m25p_probe(struct spi_device
  130. if (data)
  131. flash->max_transfer_len = data->max_transfer_len;
  132. diff --git a/target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch b/target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch
  133. deleted file mode 100644
  134. index 4d0403b..0000000
  135. --- a/target/linux/generic/patches-3.18/043-mtd_GD25Q128B_support_backport_from_3.19.patch
  136. +++ /dev/null
  137. @@ -1,10 +0,0 @@
  138. ---- a/drivers/mtd/spi-nor/spi-nor.c
  139. -+++ b/drivers/mtd/spi-nor/spi-nor.c
  140. -@@ -510,6 +510,7 @@ static const struct spi_device_id spi_no
  141. - /* GigaDevice */
  142. - { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
  143. - { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
  144. -+ { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
  145. -
  146. - /* Intel/Numonyx -- xxxs33b */
  147. - { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
  148. diff --git a/target/linux/generic/patches-3.18/093-m25p80_spi-nor_update_to_4.4.9.patch b/target/linux/generic/patches-3.18/093-m25p80_spi-nor_update_to_4.4.9.patch
  149. new file mode 100644
  150. index 0000000..5f74d3a
  151. --- /dev/null
  152. +++ b/target/linux/generic/patches-3.18/093-m25p80_spi-nor_update_to_4.4.9.patch
  153. @@ -0,0 +1,1579 @@
  154. +--- a/drivers/mtd/devices/m25p80.c
  155. ++++ b/drivers/mtd/devices/m25p80.c
  156. +@@ -31,7 +31,6 @@
  157. + struct m25p {
  158. + struct spi_device *spi;
  159. + struct spi_nor spi_nor;
  160. +- struct mtd_info mtd;
  161. + u8 command[MAX_CMD_SIZE];
  162. + };
  163. +
  164. +@@ -62,8 +61,7 @@ static int m25p_cmdsz(struct spi_nor *no
  165. + return 1 + nor->addr_width;
  166. + }
  167. +
  168. +-static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
  169. +- int wr_en)
  170. ++static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
  171. + {
  172. + struct m25p *flash = nor->priv;
  173. + struct spi_device *spi = flash->spi;
  174. +@@ -128,13 +126,10 @@ static int m25p80_read(struct spi_nor *n
  175. + struct spi_device *spi = flash->spi;
  176. + struct spi_transfer t[2];
  177. + struct spi_message m;
  178. +- int dummy = nor->read_dummy;
  179. +- int ret;
  180. ++ unsigned int dummy = nor->read_dummy;
  181. +
  182. +- /* Wait till previous write/erase is done. */
  183. +- ret = nor->wait_till_ready(nor);
  184. +- if (ret)
  185. +- return ret;
  186. ++ /* convert the dummy cycles to the number of bytes */
  187. ++ dummy /= 8;
  188. +
  189. + spi_message_init(&m);
  190. + memset(t, 0, (sizeof t));
  191. +@@ -160,20 +155,9 @@ static int m25p80_read(struct spi_nor *n
  192. + static int m25p80_erase(struct spi_nor *nor, loff_t offset)
  193. + {
  194. + struct m25p *flash = nor->priv;
  195. +- int ret;
  196. +
  197. + dev_dbg(nor->dev, "%dKiB at 0x%08x\n",
  198. +- flash->mtd.erasesize / 1024, (u32)offset);
  199. +-
  200. +- /* Wait until finished previous write command. */
  201. +- ret = nor->wait_till_ready(nor);
  202. +- if (ret)
  203. +- return ret;
  204. +-
  205. +- /* Send write enable, then erase commands. */
  206. +- ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
  207. +- if (ret)
  208. +- return ret;
  209. ++ flash->spi_nor.mtd.erasesize / 1024, (u32)offset);
  210. +
  211. + /* Set up command buffer. */
  212. + flash->command[0] = nor->erase_opcode;
  213. +@@ -215,11 +199,10 @@ static int m25p_probe(struct spi_device
  214. + nor->read_reg = m25p80_read_reg;
  215. +
  216. + nor->dev = &spi->dev;
  217. +- nor->mtd = &flash->mtd;
  218. ++ nor->flash_node = spi->dev.of_node;
  219. + nor->priv = flash;
  220. +
  221. + spi_set_drvdata(spi, flash);
  222. +- flash->mtd.priv = nor;
  223. + flash->spi = spi;
  224. +
  225. + if (spi->mode & SPI_RX_QUAD)
  226. +@@ -228,7 +211,7 @@ static int m25p_probe(struct spi_device
  227. + mode = SPI_NOR_DUAL;
  228. +
  229. + if (data && data->name)
  230. +- flash->mtd.name = data->name;
  231. ++ nor->mtd.name = data->name;
  232. +
  233. + /* For some (historical?) reason many platforms provide two different
  234. + * names in flash_platform_data: "name" and "type". Quite often name is
  235. +@@ -246,7 +229,7 @@ static int m25p_probe(struct spi_device
  236. +
  237. + ppdata.of_node = spi->dev.of_node;
  238. +
  239. +- return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
  240. ++ return mtd_device_parse_register(&nor->mtd, NULL, &ppdata,
  241. + data ? data->parts : NULL,
  242. + data ? data->nr_parts : 0);
  243. + }
  244. +@@ -257,64 +240,68 @@ static int m25p_remove(struct spi_device
  245. + struct m25p *flash = spi_get_drvdata(spi);
  246. +
  247. + /* Clean up MTD stuff. */
  248. +- return mtd_device_unregister(&flash->mtd);
  249. ++ return mtd_device_unregister(&flash->spi_nor.mtd);
  250. + }
  251. +
  252. +-
  253. + /*
  254. +- * XXX This needs to be kept in sync with spi_nor_ids. We can't share
  255. +- * it with spi-nor, because if this is built as a module then modpost
  256. +- * won't be able to read it and add appropriate aliases.
  257. ++ * Do NOT add to this array without reading the following:
  258. ++ *
  259. ++ * Historically, many flash devices are bound to this driver by their name. But
  260. ++ * since most of these flash are compatible to some extent, and their
  261. ++ * differences can often be differentiated by the JEDEC read-ID command, we
  262. ++ * encourage new users to add support to the spi-nor library, and simply bind
  263. ++ * against a generic string here (e.g., "jedec,spi-nor").
  264. ++ *
  265. ++ * Many flash names are kept here in this list (as well as in spi-nor.c) to
  266. ++ * keep them available as module aliases for existing platforms.
  267. + */
  268. + static const struct spi_device_id m25p_ids[] = {
  269. +- {"at25fs010"}, {"at25fs040"}, {"at25df041a"}, {"at25df321a"},
  270. +- {"at25df641"}, {"at26f004"}, {"at26df081a"}, {"at26df161a"},
  271. +- {"at26df321"}, {"at45db081d"},
  272. +- {"en25f32"}, {"en25p32"}, {"en25q32b"}, {"en25p64"},
  273. +- {"en25q64"}, {"en25qh128"}, {"en25qh256"},
  274. +- {"f25l32pa"},
  275. +- {"mr25h256"}, {"mr25h10"},
  276. +- {"gd25q32"}, {"gd25q64"},
  277. +- {"160s33b"}, {"320s33b"}, {"640s33b"},
  278. +- {"mx25l2005a"}, {"mx25l4005a"}, {"mx25l8005"}, {"mx25l1606e"},
  279. +- {"mx25l3205d"}, {"mx25l3255e"}, {"mx25l6405d"}, {"mx25l12805d"},
  280. +- {"mx25l12855e"},{"mx25l25635e"},{"mx25l25655e"},{"mx66l51235l"},
  281. +- {"mx66l1g55g"},
  282. +- {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q256a"},
  283. +- {"n25q512a"}, {"n25q512ax3"}, {"n25q00"},
  284. +- {"pm25lv512"}, {"pm25lv010"}, {"pm25lq032"},
  285. +- {"s25sl032p"}, {"s25sl064p"}, {"s25fl256s0"}, {"s25fl256s1"},
  286. +- {"s25fl512s"}, {"s70fl01gs"}, {"s25sl12800"}, {"s25sl12801"},
  287. +- {"s25fl129p0"}, {"s25fl129p1"}, {"s25sl004a"}, {"s25sl008a"},
  288. +- {"s25sl016a"}, {"s25sl032a"}, {"s25sl064a"}, {"s25fl008k"},
  289. +- {"s25fl016k"}, {"s25fl064k"},
  290. +- {"sst25vf040b"},{"sst25vf080b"},{"sst25vf016b"},{"sst25vf032b"},
  291. +- {"sst25vf064c"},{"sst25wf512"}, {"sst25wf010"}, {"sst25wf020"},
  292. +- {"sst25wf040"},
  293. +- {"m25p05"}, {"m25p10"}, {"m25p20"}, {"m25p40"},
  294. +- {"m25p80"}, {"m25p16"}, {"m25p32"}, {"m25p64"},
  295. +- {"m25p128"}, {"n25q032"},
  296. ++ /*
  297. ++ * Entries not used in DTs that should be safe to drop after replacing
  298. ++ * them with "nor-jedec" in platform data.
  299. ++ */
  300. ++ {"s25sl064a"}, {"w25x16"}, {"m25p10"}, {"m25px64"},
  301. ++
  302. ++ /*
  303. ++ * Entries that were used in DTs without "nor-jedec" fallback and should
  304. ++ * be kept for backward compatibility.
  305. ++ */
  306. ++ {"at25df321a"}, {"at25df641"}, {"at26df081a"},
  307. ++ {"mr25h256"},
  308. ++ {"mx25l4005a"}, {"mx25l1606e"}, {"mx25l6405d"}, {"mx25l12805d"},
  309. ++ {"mx25l25635e"},{"mx66l51235l"},
  310. ++ {"n25q064"}, {"n25q128a11"}, {"n25q128a13"}, {"n25q512a"},
  311. ++ {"s25fl256s1"}, {"s25fl512s"}, {"s25sl12801"}, {"s25fl008k"},
  312. ++ {"s25fl064k"},
  313. ++ {"sst25vf040b"},{"sst25vf016b"},{"sst25vf032b"},{"sst25wf040"},
  314. ++ {"m25p40"}, {"m25p80"}, {"m25p16"}, {"m25p32"},
  315. ++ {"m25p64"}, {"m25p128"},
  316. ++ {"w25x80"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
  317. ++ {"w25q80bl"}, {"w25q128"}, {"w25q256"},
  318. ++
  319. ++ /* Flashes that can't be detected using JEDEC */
  320. + {"m25p05-nonjedec"}, {"m25p10-nonjedec"}, {"m25p20-nonjedec"},
  321. + {"m25p40-nonjedec"}, {"m25p80-nonjedec"}, {"m25p16-nonjedec"},
  322. + {"m25p32-nonjedec"}, {"m25p64-nonjedec"}, {"m25p128-nonjedec"},
  323. +- {"m45pe10"}, {"m45pe80"}, {"m45pe16"},
  324. +- {"m25pe20"}, {"m25pe80"}, {"m25pe16"},
  325. +- {"m25px16"}, {"m25px32"}, {"m25px32-s0"}, {"m25px32-s1"},
  326. +- {"m25px64"}, {"m25px80"},
  327. +- {"w25x10"}, {"w25x20"}, {"w25x40"}, {"w25x80"},
  328. +- {"w25x16"}, {"w25x32"}, {"w25q32"}, {"w25q32dw"},
  329. +- {"w25x64"}, {"w25q64"}, {"w25q80"}, {"w25q80bl"},
  330. +- {"w25q128"}, {"w25q256"}, {"cat25c11"},
  331. +- {"cat25c03"}, {"cat25c09"}, {"cat25c17"}, {"cat25128"},
  332. ++
  333. + { },
  334. + };
  335. + MODULE_DEVICE_TABLE(spi, m25p_ids);
  336. +
  337. ++static const struct of_device_id m25p_of_table[] = {
  338. ++ /*
  339. ++ * Generic compatibility for SPI NOR that can be identified by the
  340. ++ * JEDEC READ ID opcode (0x9F). Use this, if possible.
  341. ++ */
  342. ++ { .compatible = "jedec,spi-nor" },
  343. ++ {}
  344. ++};
  345. ++MODULE_DEVICE_TABLE(of, m25p_of_table);
  346. +
  347. + static struct spi_driver m25p80_driver = {
  348. + .driver = {
  349. + .name = "m25p80",
  350. +- .owner = THIS_MODULE,
  351. ++ .of_match_table = m25p_of_table,
  352. + },
  353. + .id_table = m25p_ids,
  354. + .probe = m25p_probe,
  355. +--- a/drivers/mtd/spi-nor/spi-nor.c
  356. ++++ b/drivers/mtd/spi-nor/spi-nor.c
  357. +@@ -16,19 +16,63 @@
  358. + #include <linux/device.h>
  359. + #include <linux/mutex.h>
  360. + #include <linux/math64.h>
  361. ++#include <linux/sizes.h>
  362. +
  363. +-#include <linux/mtd/cfi.h>
  364. + #include <linux/mtd/mtd.h>
  365. + #include <linux/of_platform.h>
  366. + #include <linux/spi/flash.h>
  367. + #include <linux/mtd/spi-nor.h>
  368. +
  369. + /* Define max times to check status register before we give up. */
  370. +-#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
  371. +
  372. +-#define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
  373. ++/*
  374. ++ * For everything but full-chip erase; probably could be much smaller, but kept
  375. ++ * around for safety for now
  376. ++ */
  377. ++#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
  378. ++
  379. ++/*
  380. ++ * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
  381. ++ * for larger flash
  382. ++ */
  383. ++#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES (40UL * HZ)
  384. ++
  385. ++#define SPI_NOR_MAX_ID_LEN 6
  386. ++
  387. ++struct flash_info {
  388. ++ char *name;
  389. ++
  390. ++ /*
  391. ++ * This array stores the ID bytes.
  392. ++ * The first three bytes are the JEDIC ID.
  393. ++ * JEDEC ID zero means "no ID" (mostly older chips).
  394. ++ */
  395. ++ u8 id[SPI_NOR_MAX_ID_LEN];
  396. ++ u8 id_len;
  397. ++
  398. ++ /* The size listed here is what works with SPINOR_OP_SE, which isn't
  399. ++ * necessarily called a "sector" by the vendor.
  400. ++ */
  401. ++ unsigned sector_size;
  402. ++ u16 n_sectors;
  403. ++
  404. ++ u16 page_size;
  405. ++ u16 addr_width;
  406. ++
  407. ++ u16 flags;
  408. ++#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
  409. ++#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
  410. ++#define SST_WRITE 0x04 /* use SST byte programming */
  411. ++#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
  412. ++#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
  413. ++#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
  414. ++#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
  415. ++#define USE_FSR 0x80 /* use flag status register */
  416. ++};
  417. +
  418. +-static const struct spi_device_id *spi_nor_match_id(const char *name);
  419. ++#define JEDEC_MFR(info) ((info)->id[0])
  420. ++
  421. ++static const struct flash_info *spi_nor_match_id(const char *name);
  422. +
  423. + /*
  424. + * Read the status register, returning its value in the location
  425. +@@ -98,7 +142,7 @@ static inline int spi_nor_read_dummy_cyc
  426. + case SPI_NOR_FAST:
  427. + case SPI_NOR_DUAL:
  428. + case SPI_NOR_QUAD:
  429. +- return 1;
  430. ++ return 8;
  431. + case SPI_NOR_NORMAL:
  432. + return 0;
  433. + }
  434. +@@ -112,7 +156,7 @@ static inline int spi_nor_read_dummy_cyc
  435. + static inline int write_sr(struct spi_nor *nor, u8 val)
  436. + {
  437. + nor->cmd_buf[0] = val;
  438. +- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
  439. ++ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
  440. + }
  441. +
  442. + /*
  443. +@@ -121,7 +165,7 @@ static inline int write_sr(struct spi_no
  444. + */
  445. + static inline int write_enable(struct spi_nor *nor)
  446. + {
  447. +- return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
  448. ++ return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
  449. + }
  450. +
  451. + /*
  452. +@@ -129,7 +173,7 @@ static inline int write_enable(struct sp
  453. + */
  454. + static inline int write_disable(struct spi_nor *nor)
  455. + {
  456. +- return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
  457. ++ return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
  458. + }
  459. +
  460. + static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
  461. +@@ -138,23 +182,24 @@ static inline struct spi_nor *mtd_to_spi
  462. + }
  463. +
  464. + /* Enable/disable 4-byte addressing mode. */
  465. +-static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable)
  466. ++static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
  467. ++ int enable)
  468. + {
  469. + int status;
  470. + bool need_wren = false;
  471. + u8 cmd;
  472. +
  473. +- switch (JEDEC_MFR(jedec_id)) {
  474. +- case CFI_MFR_ST: /* Micron, actually */
  475. ++ switch (JEDEC_MFR(info)) {
  476. ++ case SNOR_MFR_MICRON:
  477. + /* Some Micron need WREN command; all will accept it */
  478. + need_wren = true;
  479. +- case CFI_MFR_MACRONIX:
  480. +- case 0xEF /* winbond */:
  481. ++ case SNOR_MFR_MACRONIX:
  482. ++ case SNOR_MFR_WINBOND:
  483. + if (need_wren)
  484. + write_enable(nor);
  485. +
  486. + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
  487. +- status = nor->write_reg(nor, cmd, NULL, 0, 0);
  488. ++ status = nor->write_reg(nor, cmd, NULL, 0);
  489. + if (need_wren)
  490. + write_disable(nor);
  491. +
  492. +@@ -162,63 +207,73 @@ static inline int set_4byte(struct spi_n
  493. + default:
  494. + /* Spansion style */
  495. + nor->cmd_buf[0] = enable << 7;
  496. +- return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
  497. ++ return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
  498. + }
  499. + }
  500. +-
  501. +-static int spi_nor_wait_till_ready(struct spi_nor *nor)
  502. ++static inline int spi_nor_sr_ready(struct spi_nor *nor)
  503. + {
  504. +- unsigned long deadline;
  505. +- int sr;
  506. +-
  507. +- deadline = jiffies + MAX_READY_WAIT_JIFFIES;
  508. +-
  509. +- do {
  510. +- cond_resched();
  511. ++ int sr = read_sr(nor);
  512. ++ if (sr < 0)
  513. ++ return sr;
  514. ++ else
  515. ++ return !(sr & SR_WIP);
  516. ++}
  517. +
  518. +- sr = read_sr(nor);
  519. +- if (sr < 0)
  520. +- break;
  521. +- else if (!(sr & SR_WIP))
  522. +- return 0;
  523. +- } while (!time_after_eq(jiffies, deadline));
  524. ++static inline int spi_nor_fsr_ready(struct spi_nor *nor)
  525. ++{
  526. ++ int fsr = read_fsr(nor);
  527. ++ if (fsr < 0)
  528. ++ return fsr;
  529. ++ else
  530. ++ return fsr & FSR_READY;
  531. ++}
  532. +
  533. +- return -ETIMEDOUT;
  534. ++static int spi_nor_ready(struct spi_nor *nor)
  535. ++{
  536. ++ int sr, fsr;
  537. ++ sr = spi_nor_sr_ready(nor);
  538. ++ if (sr < 0)
  539. ++ return sr;
  540. ++ fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1;
  541. ++ if (fsr < 0)
  542. ++ return fsr;
  543. ++ return sr && fsr;
  544. + }
  545. +
  546. +-static int spi_nor_wait_till_fsr_ready(struct spi_nor *nor)
  547. ++/*
  548. ++ * Service routine to read status register until ready, or timeout occurs.
  549. ++ * Returns non-zero if error.
  550. ++ */
  551. ++static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
  552. ++ unsigned long timeout_jiffies)
  553. + {
  554. + unsigned long deadline;
  555. +- int sr;
  556. +- int fsr;
  557. ++ int timeout = 0, ret;
  558. +
  559. +- deadline = jiffies + MAX_READY_WAIT_JIFFIES;
  560. ++ deadline = jiffies + timeout_jiffies;
  561. ++
  562. ++ while (!timeout) {
  563. ++ if (time_after_eq(jiffies, deadline))
  564. ++ timeout = 1;
  565. ++
  566. ++ ret = spi_nor_ready(nor);
  567. ++ if (ret < 0)
  568. ++ return ret;
  569. ++ if (ret)
  570. ++ return 0;
  571. +
  572. +- do {
  573. + cond_resched();
  574. ++ }
  575. +
  576. +- sr = read_sr(nor);
  577. +- if (sr < 0) {
  578. +- break;
  579. +- } else if (!(sr & SR_WIP)) {
  580. +- fsr = read_fsr(nor);
  581. +- if (fsr < 0)
  582. +- break;
  583. +- if (fsr & FSR_READY)
  584. +- return 0;
  585. +- }
  586. +- } while (!time_after_eq(jiffies, deadline));
  587. ++ dev_err(nor->dev, "flash operation timed out\n");
  588. +
  589. + return -ETIMEDOUT;
  590. + }
  591. +
  592. +-/*
  593. +- * Service routine to read status register until ready, or timeout occurs.
  594. +- * Returns non-zero if error.
  595. +- */
  596. +-static int wait_till_ready(struct spi_nor *nor)
  597. ++static int spi_nor_wait_till_ready(struct spi_nor *nor)
  598. + {
  599. +- return nor->wait_till_ready(nor);
  600. ++ return spi_nor_wait_till_ready_with_timeout(nor,
  601. ++ DEFAULT_READY_WAIT_JIFFIES);
  602. + }
  603. +
  604. + /*
  605. +@@ -228,19 +283,9 @@ static int wait_till_ready(struct spi_no
  606. + */
  607. + static int erase_chip(struct spi_nor *nor)
  608. + {
  609. +- int ret;
  610. +-
  611. +- dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
  612. ++ dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
  613. +
  614. +- /* Wait until finished previous write command. */
  615. +- ret = wait_till_ready(nor);
  616. +- if (ret)
  617. +- return ret;
  618. +-
  619. +- /* Send write enable, then erase commands. */
  620. +- write_enable(nor);
  621. +-
  622. +- return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
  623. ++ return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
  624. + }
  625. +
  626. + static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
  627. +@@ -294,11 +339,28 @@ static int spi_nor_erase(struct mtd_info
  628. +
  629. + /* whole-chip erase? */
  630. + if (len == mtd->size) {
  631. ++ unsigned long timeout;
  632. ++
  633. ++ write_enable(nor);
  634. ++
  635. + if (erase_chip(nor)) {
  636. + ret = -EIO;
  637. + goto erase_err;
  638. + }
  639. +
  640. ++ /*
  641. ++ * Scale the timeout linearly with the size of the flash, with
  642. ++ * a minimum calibrated to an old 2MB flash. We could try to
  643. ++ * pull these from CFI/SFDP, but these values should be good
  644. ++ * enough for now.
  645. ++ */
  646. ++ timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
  647. ++ CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
  648. ++ (unsigned long)(mtd->size / SZ_2M));
  649. ++ ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
  650. ++ if (ret)
  651. ++ goto erase_err;
  652. ++
  653. + /* REVISIT in some cases we could speed up erasing large regions
  654. + * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
  655. + * to use "small sector erase", but that's not always optimal.
  656. +@@ -307,6 +369,8 @@ static int spi_nor_erase(struct mtd_info
  657. + /* "sector"-at-a-time erase */
  658. + } else {
  659. + while (len) {
  660. ++ write_enable(nor);
  661. ++
  662. + if (nor->erase(nor, addr)) {
  663. + ret = -EIO;
  664. + goto erase_err;
  665. +@@ -314,9 +378,15 @@ static int spi_nor_erase(struct mtd_info
  666. +
  667. + addr += mtd->erasesize;
  668. + len -= mtd->erasesize;
  669. ++
  670. ++ ret = spi_nor_wait_till_ready(nor);
  671. ++ if (ret)
  672. ++ goto erase_err;
  673. + }
  674. + }
  675. +
  676. ++ write_disable(nor);
  677. ++
  678. + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
  679. +
  680. + instr->state = MTD_ERASE_DONE;
  681. +@@ -330,152 +400,267 @@ erase_err:
  682. + return ret;
  683. + }
  684. +
  685. +-static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  686. ++static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
  687. ++ uint64_t *len)
  688. + {
  689. +- struct spi_nor *nor = mtd_to_spi_nor(mtd);
  690. +- uint32_t offset = ofs;
  691. +- uint8_t status_old, status_new;
  692. +- int ret = 0;
  693. ++ struct mtd_info *mtd = &nor->mtd;
  694. ++ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  695. ++ int shift = ffs(mask) - 1;
  696. ++ int pow;
  697. ++
  698. ++ if (!(sr & mask)) {
  699. ++ /* No protection */
  700. ++ *ofs = 0;
  701. ++ *len = 0;
  702. ++ } else {
  703. ++ pow = ((sr & mask) ^ mask) >> shift;
  704. ++ *len = mtd->size >> pow;
  705. ++ *ofs = mtd->size - *len;
  706. ++ }
  707. ++}
  708. +
  709. +- ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
  710. +- if (ret)
  711. +- return ret;
  712. ++/*
  713. ++ * Return 1 if the entire region is locked, 0 otherwise
  714. ++ */
  715. ++static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len,
  716. ++ u8 sr)
  717. ++{
  718. ++ loff_t lock_offs;
  719. ++ uint64_t lock_len;
  720. +
  721. +- /* Wait until finished previous command */
  722. +- ret = wait_till_ready(nor);
  723. +- if (ret)
  724. +- goto err;
  725. ++ stm_get_locked_range(nor, sr, &lock_offs, &lock_len);
  726. ++
  727. ++ return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs);
  728. ++}
  729. ++
  730. ++/*
  731. ++ * Lock a region of the flash. Compatible with ST Micro and similar flash.
  732. ++ * Supports only the block protection bits BP{0,1,2} in the status register
  733. ++ * (SR). Does not support these features found in newer SR bitfields:
  734. ++ * - TB: top/bottom protect - only handle TB=0 (top protect)
  735. ++ * - SEC: sector/block protect - only handle SEC=0 (block protect)
  736. ++ * - CMP: complement protect - only support CMP=0 (range is not complemented)
  737. ++ *
  738. ++ * Sample table portion for 8MB flash (Winbond w25q64fw):
  739. ++ *
  740. ++ * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion
  741. ++ * --------------------------------------------------------------------------
  742. ++ * X | X | 0 | 0 | 0 | NONE | NONE
  743. ++ * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64
  744. ++ * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32
  745. ++ * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16
  746. ++ * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8
  747. ++ * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4
  748. ++ * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2
  749. ++ * X | X | 1 | 1 | 1 | 8 MB | ALL
  750. ++ *
  751. ++ * Returns negative on errors, 0 on success.
  752. ++ */
  753. ++static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  754. ++{
  755. ++ struct mtd_info *mtd = &nor->mtd;
  756. ++ u8 status_old, status_new;
  757. ++ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  758. ++ u8 shift = ffs(mask) - 1, pow, val;
  759. +
  760. + status_old = read_sr(nor);
  761. +
  762. +- if (offset < mtd->size - (mtd->size / 2))
  763. +- status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
  764. +- else if (offset < mtd->size - (mtd->size / 4))
  765. +- status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
  766. +- else if (offset < mtd->size - (mtd->size / 8))
  767. +- status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
  768. +- else if (offset < mtd->size - (mtd->size / 16))
  769. +- status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
  770. +- else if (offset < mtd->size - (mtd->size / 32))
  771. +- status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
  772. +- else if (offset < mtd->size - (mtd->size / 64))
  773. +- status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
  774. +- else
  775. +- status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
  776. ++ /* SPI NOR always locks to the end */
  777. ++ if (ofs + len != mtd->size) {
  778. ++ /* Does combined region extend to end? */
  779. ++ if (!stm_is_locked_sr(nor, ofs + len, mtd->size - ofs - len,
  780. ++ status_old))
  781. ++ return -EINVAL;
  782. ++ len = mtd->size - ofs;
  783. ++ }
  784. ++
  785. ++ /*
  786. ++ * Need smallest pow such that:
  787. ++ *
  788. ++ * 1 / (2^pow) <= (len / size)
  789. ++ *
  790. ++ * so (assuming power-of-2 size) we do:
  791. ++ *
  792. ++ * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
  793. ++ */
  794. ++ pow = ilog2(mtd->size) - ilog2(len);
  795. ++ val = mask - (pow << shift);
  796. ++ if (val & ~mask)
  797. ++ return -EINVAL;
  798. ++ /* Don't "lock" with no region! */
  799. ++ if (!(val & mask))
  800. ++ return -EINVAL;
  801. ++
  802. ++ status_new = (status_old & ~mask) | val;
  803. +
  804. + /* Only modify protection if it will not unlock other areas */
  805. +- if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
  806. +- (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
  807. +- write_enable(nor);
  808. +- ret = write_sr(nor, status_new);
  809. +- if (ret)
  810. +- goto err;
  811. ++ if ((status_new & mask) <= (status_old & mask))
  812. ++ return -EINVAL;
  813. ++
  814. ++ write_enable(nor);
  815. ++ return write_sr(nor, status_new);
  816. ++}
  817. ++
  818. ++/*
  819. ++ * Unlock a region of the flash. See stm_lock() for more info
  820. ++ *
  821. ++ * Returns negative on errors, 0 on success.
  822. ++ */
  823. ++static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
  824. ++{
  825. ++ struct mtd_info *mtd = &nor->mtd;
  826. ++ uint8_t status_old, status_new;
  827. ++ u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
  828. ++ u8 shift = ffs(mask) - 1, pow, val;
  829. ++
  830. ++ status_old = read_sr(nor);
  831. ++
  832. ++ /* Cannot unlock; would unlock larger region than requested */
  833. ++ if (stm_is_locked_sr(nor, ofs - mtd->erasesize, mtd->erasesize,
  834. ++ status_old))
  835. ++ return -EINVAL;
  836. ++
  837. ++ /*
  838. ++ * Need largest pow such that:
  839. ++ *
  840. ++ * 1 / (2^pow) >= (len / size)
  841. ++ *
  842. ++ * so (assuming power-of-2 size) we do:
  843. ++ *
  844. ++ * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len))
  845. ++ */
  846. ++ pow = ilog2(mtd->size) - order_base_2(mtd->size - (ofs + len));
  847. ++ if (ofs + len == mtd->size) {
  848. ++ val = 0; /* fully unlocked */
  849. ++ } else {
  850. ++ val = mask - (pow << shift);
  851. ++ /* Some power-of-two sizes are not supported */
  852. ++ if (val & ~mask)
  853. ++ return -EINVAL;
  854. + }
  855. +
  856. +-err:
  857. +- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
  858. +- return ret;
  859. ++ status_new = (status_old & ~mask) | val;
  860. ++
  861. ++ /* Only modify protection if it will not lock other areas */
  862. ++ if ((status_new & mask) >= (status_old & mask))
  863. ++ return -EINVAL;
  864. ++
  865. ++ write_enable(nor);
  866. ++ return write_sr(nor, status_new);
  867. + }
  868. +
  869. +-static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  870. ++/*
  871. ++ * Check if a region of the flash is (completely) locked. See stm_lock() for
  872. ++ * more info.
  873. ++ *
  874. ++ * Returns 1 if entire region is locked, 0 if any portion is unlocked, and
  875. ++ * negative on errors.
  876. ++ */
  877. ++static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
  878. ++{
  879. ++ int status;
  880. ++
  881. ++ status = read_sr(nor);
  882. ++ if (status < 0)
  883. ++ return status;
  884. ++
  885. ++ return stm_is_locked_sr(nor, ofs, len, status);
  886. ++}
  887. ++
  888. ++static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  889. + {
  890. + struct spi_nor *nor = mtd_to_spi_nor(mtd);
  891. +- uint32_t offset = ofs;
  892. +- uint8_t status_old, status_new;
  893. +- int ret = 0;
  894. ++ int ret;
  895. +
  896. +- ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
  897. ++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
  898. + if (ret)
  899. + return ret;
  900. +
  901. +- /* Wait until finished previous command */
  902. +- ret = wait_till_ready(nor);
  903. +- if (ret)
  904. +- goto err;
  905. ++ ret = nor->flash_lock(nor, ofs, len);
  906. +
  907. +- status_old = read_sr(nor);
  908. ++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
  909. ++ return ret;
  910. ++}
  911. +
  912. +- if (offset+len > mtd->size - (mtd->size / 64))
  913. +- status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
  914. +- else if (offset+len > mtd->size - (mtd->size / 32))
  915. +- status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
  916. +- else if (offset+len > mtd->size - (mtd->size / 16))
  917. +- status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
  918. +- else if (offset+len > mtd->size - (mtd->size / 8))
  919. +- status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
  920. +- else if (offset+len > mtd->size - (mtd->size / 4))
  921. +- status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
  922. +- else if (offset+len > mtd->size - (mtd->size / 2))
  923. +- status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
  924. +- else
  925. +- status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
  926. ++static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  927. ++{
  928. ++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
  929. ++ int ret;
  930. +
  931. +- /* Only modify protection if it will not lock other areas */
  932. +- if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
  933. +- (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
  934. +- write_enable(nor);
  935. +- ret = write_sr(nor, status_new);
  936. +- if (ret)
  937. +- goto err;
  938. +- }
  939. ++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
  940. ++ if (ret)
  941. ++ return ret;
  942. +
  943. +-err:
  944. +- spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
  945. ++ ret = nor->flash_unlock(nor, ofs, len);
  946. ++
  947. ++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
  948. + return ret;
  949. + }
  950. +
  951. +-struct flash_info {
  952. +- /* JEDEC id zero means "no ID" (most older chips); otherwise it has
  953. +- * a high byte of zero plus three data bytes: the manufacturer id,
  954. +- * then a two byte device id.
  955. +- */
  956. +- u32 jedec_id;
  957. +- u16 ext_id;
  958. ++static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len)
  959. ++{
  960. ++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
  961. ++ int ret;
  962. +
  963. +- /* The size listed here is what works with SPINOR_OP_SE, which isn't
  964. +- * necessarily called a "sector" by the vendor.
  965. +- */
  966. +- unsigned sector_size;
  967. +- u16 n_sectors;
  968. ++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
  969. ++ if (ret)
  970. ++ return ret;
  971. +
  972. +- u16 page_size;
  973. +- u16 addr_width;
  974. ++ ret = nor->flash_is_locked(nor, ofs, len);
  975. +
  976. +- u16 flags;
  977. +-#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
  978. +-#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
  979. +-#define SST_WRITE 0x04 /* use SST byte programming */
  980. +-#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
  981. +-#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
  982. +-#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
  983. +-#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
  984. +-#define USE_FSR 0x80 /* use flag status register */
  985. +-};
  986. ++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
  987. ++ return ret;
  988. ++}
  989. +
  990. ++/* Used when the "_ext_id" is two bytes at most */
  991. + #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
  992. +- ((kernel_ulong_t)&(struct flash_info) { \
  993. +- .jedec_id = (_jedec_id), \
  994. +- .ext_id = (_ext_id), \
  995. ++ .id = { \
  996. ++ ((_jedec_id) >> 16) & 0xff, \
  997. ++ ((_jedec_id) >> 8) & 0xff, \
  998. ++ (_jedec_id) & 0xff, \
  999. ++ ((_ext_id) >> 8) & 0xff, \
  1000. ++ (_ext_id) & 0xff, \
  1001. ++ }, \
  1002. ++ .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \
  1003. ++ .sector_size = (_sector_size), \
  1004. ++ .n_sectors = (_n_sectors), \
  1005. ++ .page_size = 256, \
  1006. ++ .flags = (_flags),
  1007. ++
  1008. ++#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
  1009. ++ .id = { \
  1010. ++ ((_jedec_id) >> 16) & 0xff, \
  1011. ++ ((_jedec_id) >> 8) & 0xff, \
  1012. ++ (_jedec_id) & 0xff, \
  1013. ++ ((_ext_id) >> 16) & 0xff, \
  1014. ++ ((_ext_id) >> 8) & 0xff, \
  1015. ++ (_ext_id) & 0xff, \
  1016. ++ }, \
  1017. ++ .id_len = 6, \
  1018. + .sector_size = (_sector_size), \
  1019. + .n_sectors = (_n_sectors), \
  1020. + .page_size = 256, \
  1021. +- .flags = (_flags), \
  1022. +- })
  1023. ++ .flags = (_flags),
  1024. +
  1025. + #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
  1026. +- ((kernel_ulong_t)&(struct flash_info) { \
  1027. + .sector_size = (_sector_size), \
  1028. + .n_sectors = (_n_sectors), \
  1029. + .page_size = (_page_size), \
  1030. + .addr_width = (_addr_width), \
  1031. +- .flags = (_flags), \
  1032. +- })
  1033. ++ .flags = (_flags),
  1034. +
  1035. + /* NOTE: double check command sets and memory organization when you add
  1036. + * more nor chips. This current list focusses on newer chips, which
  1037. + * have been converging on command sets which including JEDEC ID.
  1038. ++ *
  1039. ++ * All newly added entries should describe *hardware* and should use SECT_4K
  1040. ++ * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
  1041. ++ * scenarios excluding small sectors there is config option that can be
  1042. ++ * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
  1043. ++ * For historical (and compatibility) reasons (before we got above config) some
  1044. ++ * old entries may be missing 4K flag.
  1045. + */
  1046. +-static const struct spi_device_id spi_nor_ids[] = {
  1047. ++static const struct flash_info spi_nor_ids[] = {
  1048. + /* Atmel -- some are (confusingly) marketed as "DataFlash" */
  1049. + { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
  1050. + { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
  1051. +@@ -499,6 +684,7 @@ static const struct spi_device_id spi_no
  1052. + { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
  1053. + { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
  1054. + { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
  1055. ++ { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
  1056. +
  1057. + /* ESMT */
  1058. + { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
  1059. +@@ -507,16 +693,24 @@ static const struct spi_device_id spi_no
  1060. + { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
  1061. + { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
  1062. +
  1063. ++ /* Fujitsu */
  1064. ++ { "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
  1065. ++
  1066. + /* GigaDevice */
  1067. + { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
  1068. + { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
  1069. ++ { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
  1070. +
  1071. + /* Intel/Numonyx -- xxxs33b */
  1072. + { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
  1073. + { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
  1074. + { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
  1075. +
  1076. ++ /* ISSI */
  1077. ++ { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
  1078. ++
  1079. + /* Macronix */
  1080. ++ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
  1081. + { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
  1082. + { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
  1083. + { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
  1084. +@@ -524,6 +718,7 @@ static const struct spi_device_id spi_no
  1085. + { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
  1086. + { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
  1087. + { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
  1088. ++ { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
  1089. + { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
  1090. + { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
  1091. + { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
  1092. +@@ -532,13 +727,16 @@ static const struct spi_device_id spi_no
  1093. + { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
  1094. +
  1095. + /* Micron */
  1096. +- { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
  1097. +- { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
  1098. +- { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
  1099. +- { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
  1100. +- { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
  1101. +- { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },
  1102. +- { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },
  1103. ++ { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
  1104. ++ { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
  1105. ++ { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
  1106. ++ { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
  1107. ++ { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
  1108. ++ { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
  1109. ++ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
  1110. ++ { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
  1111. ++ { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
  1112. ++ { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
  1113. +
  1114. + /* PMC */
  1115. + { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
  1116. +@@ -549,23 +747,28 @@ static const struct spi_device_id spi_no
  1117. + * for the chips listed here (without boot sectors).
  1118. + */
  1119. + { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1120. +- { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
  1121. ++ { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1122. + { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
  1123. + { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1124. + { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1125. + { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
  1126. + { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
  1127. + { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
  1128. +- { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
  1129. +- { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
  1130. ++ { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
  1131. ++ { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1132. ++ { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1133. + { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
  1134. + { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
  1135. + { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
  1136. + { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
  1137. + { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
  1138. +- { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
  1139. +- { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
  1140. ++ { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1141. ++ { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1142. ++ { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1143. + { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
  1144. ++ { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) },
  1145. ++ { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) },
  1146. ++ { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ) },
  1147. +
  1148. + /* SST -- large erase sizes are "overlays", "sectors" are 4K */
  1149. + { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
  1150. +@@ -576,7 +779,10 @@ static const struct spi_device_id spi_no
  1151. + { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
  1152. + { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
  1153. + { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
  1154. ++ { "sst25wf020a", INFO(0x621612, 0, 64 * 1024, 4, SECT_4K) },
  1155. ++ { "sst25wf040b", INFO(0x621613, 0, 64 * 1024, 8, SECT_4K) },
  1156. + { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
  1157. ++ { "sst25wf080", INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
  1158. +
  1159. + /* ST Microelectronics -- newer production may have feature updates */
  1160. + { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
  1161. +@@ -588,7 +794,6 @@ static const struct spi_device_id spi_no
  1162. + { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
  1163. + { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
  1164. + { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
  1165. +- { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
  1166. +
  1167. + { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
  1168. + { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
  1169. +@@ -616,6 +821,7 @@ static const struct spi_device_id spi_no
  1170. + { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
  1171. +
  1172. + /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
  1173. ++ { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
  1174. + { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
  1175. + { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
  1176. + { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
  1177. +@@ -623,9 +829,11 @@ static const struct spi_device_id spi_no
  1178. + { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
  1179. + { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
  1180. + { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
  1181. +- { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
  1182. ++ { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1183. + { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
  1184. + { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
  1185. ++ { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1186. ++ { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
  1187. + { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
  1188. + { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
  1189. + { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
  1190. +@@ -640,35 +848,27 @@ static const struct spi_device_id spi_no
  1191. + { },
  1192. + };
  1193. +
  1194. +-static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
  1195. ++static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
  1196. + {
  1197. + int tmp;
  1198. +- u8 id[5];
  1199. +- u32 jedec;
  1200. +- u16 ext_jedec;
  1201. +- struct flash_info *info;
  1202. ++ u8 id[SPI_NOR_MAX_ID_LEN];
  1203. ++ const struct flash_info *info;
  1204. +
  1205. +- tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5);
  1206. ++ tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
  1207. + if (tmp < 0) {
  1208. + dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
  1209. + return ERR_PTR(tmp);
  1210. + }
  1211. +- jedec = id[0];
  1212. +- jedec = jedec << 8;
  1213. +- jedec |= id[1];
  1214. +- jedec = jedec << 8;
  1215. +- jedec |= id[2];
  1216. +-
  1217. +- ext_jedec = id[3] << 8 | id[4];
  1218. +
  1219. + for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
  1220. +- info = (void *)spi_nor_ids[tmp].driver_data;
  1221. +- if (info->jedec_id == jedec) {
  1222. +- if (info->ext_id == 0 || info->ext_id == ext_jedec)
  1223. ++ info = &spi_nor_ids[tmp];
  1224. ++ if (info->id_len) {
  1225. ++ if (!memcmp(info->id, id, info->id_len))
  1226. + return &spi_nor_ids[tmp];
  1227. + }
  1228. + }
  1229. +- dev_err(nor->dev, "unrecognized JEDEC id %06x\n", jedec);
  1230. ++ dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %2x, %2x\n",
  1231. ++ id[0], id[1], id[2]);
  1232. + return ERR_PTR(-ENODEV);
  1233. + }
  1234. +
  1235. +@@ -703,11 +903,6 @@ static int sst_write(struct mtd_info *mt
  1236. + if (ret)
  1237. + return ret;
  1238. +
  1239. +- /* Wait until finished previous write command. */
  1240. +- ret = wait_till_ready(nor);
  1241. +- if (ret)
  1242. +- goto time_out;
  1243. +-
  1244. + write_enable(nor);
  1245. +
  1246. + nor->sst_write_second = false;
  1247. +@@ -719,7 +914,7 @@ static int sst_write(struct mtd_info *mt
  1248. +
  1249. + /* write one byte. */
  1250. + nor->write(nor, to, 1, retlen, buf);
  1251. +- ret = wait_till_ready(nor);
  1252. ++ ret = spi_nor_wait_till_ready(nor);
  1253. + if (ret)
  1254. + goto time_out;
  1255. + }
  1256. +@@ -731,7 +926,7 @@ static int sst_write(struct mtd_info *mt
  1257. +
  1258. + /* write two bytes. */
  1259. + nor->write(nor, to, 2, retlen, buf + actual);
  1260. +- ret = wait_till_ready(nor);
  1261. ++ ret = spi_nor_wait_till_ready(nor);
  1262. + if (ret)
  1263. + goto time_out;
  1264. + to += 2;
  1265. +@@ -740,7 +935,7 @@ static int sst_write(struct mtd_info *mt
  1266. + nor->sst_write_second = false;
  1267. +
  1268. + write_disable(nor);
  1269. +- ret = wait_till_ready(nor);
  1270. ++ ret = spi_nor_wait_till_ready(nor);
  1271. + if (ret)
  1272. + goto time_out;
  1273. +
  1274. +@@ -751,7 +946,7 @@ static int sst_write(struct mtd_info *mt
  1275. + nor->program_opcode = SPINOR_OP_BP;
  1276. + nor->write(nor, to, 1, retlen, buf + actual);
  1277. +
  1278. +- ret = wait_till_ready(nor);
  1279. ++ ret = spi_nor_wait_till_ready(nor);
  1280. + if (ret)
  1281. + goto time_out;
  1282. + write_disable(nor);
  1283. +@@ -779,11 +974,6 @@ static int spi_nor_write(struct mtd_info
  1284. + if (ret)
  1285. + return ret;
  1286. +
  1287. +- /* Wait until finished previous write command. */
  1288. +- ret = wait_till_ready(nor);
  1289. +- if (ret)
  1290. +- goto write_err;
  1291. +-
  1292. + write_enable(nor);
  1293. +
  1294. + page_offset = to & (nor->page_size - 1);
  1295. +@@ -802,16 +992,20 @@ static int spi_nor_write(struct mtd_info
  1296. + if (page_size > nor->page_size)
  1297. + page_size = nor->page_size;
  1298. +
  1299. +- wait_till_ready(nor);
  1300. ++ ret = spi_nor_wait_till_ready(nor);
  1301. ++ if (ret)
  1302. ++ goto write_err;
  1303. ++
  1304. + write_enable(nor);
  1305. +
  1306. + nor->write(nor, to + i, page_size, retlen, buf + i);
  1307. + }
  1308. + }
  1309. +
  1310. ++ ret = spi_nor_wait_till_ready(nor);
  1311. + write_err:
  1312. + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
  1313. +- return 0;
  1314. ++ return ret;
  1315. + }
  1316. +
  1317. + static int macronix_quad_enable(struct spi_nor *nor)
  1318. +@@ -821,10 +1015,9 @@ static int macronix_quad_enable(struct s
  1319. + val = read_sr(nor);
  1320. + write_enable(nor);
  1321. +
  1322. +- nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
  1323. +- nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
  1324. ++ write_sr(nor, val | SR_QUAD_EN_MX);
  1325. +
  1326. +- if (wait_till_ready(nor))
  1327. ++ if (spi_nor_wait_till_ready(nor))
  1328. + return 1;
  1329. +
  1330. + ret = read_sr(nor);
  1331. +@@ -847,7 +1040,7 @@ static int write_sr_cr(struct spi_nor *n
  1332. + nor->cmd_buf[0] = val & 0xff;
  1333. + nor->cmd_buf[1] = (val >> 8);
  1334. +
  1335. +- return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
  1336. ++ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
  1337. + }
  1338. +
  1339. + static int spansion_quad_enable(struct spi_nor *nor)
  1340. +@@ -874,18 +1067,20 @@ static int spansion_quad_enable(struct s
  1341. + return 0;
  1342. + }
  1343. +
  1344. +-static int set_quad_mode(struct spi_nor *nor, u32 jedec_id)
  1345. ++static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
  1346. + {
  1347. + int status;
  1348. +
  1349. +- switch (JEDEC_MFR(jedec_id)) {
  1350. +- case CFI_MFR_MACRONIX:
  1351. ++ switch (JEDEC_MFR(info)) {
  1352. ++ case SNOR_MFR_MACRONIX:
  1353. + status = macronix_quad_enable(nor);
  1354. + if (status) {
  1355. + dev_err(nor->dev, "Macronix quad-read not enabled\n");
  1356. + return -EINVAL;
  1357. + }
  1358. + return status;
  1359. ++ case SNOR_MFR_MICRON:
  1360. ++ return 0;
  1361. + default:
  1362. + status = spansion_quad_enable(nor);
  1363. + if (status) {
  1364. +@@ -904,21 +1099,15 @@ static int spi_nor_check(struct spi_nor
  1365. + return -EINVAL;
  1366. + }
  1367. +
  1368. +- if (!nor->read_id)
  1369. +- nor->read_id = spi_nor_read_id;
  1370. +- if (!nor->wait_till_ready)
  1371. +- nor->wait_till_ready = spi_nor_wait_till_ready;
  1372. +-
  1373. + return 0;
  1374. + }
  1375. +
  1376. + int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
  1377. + {
  1378. +- const struct spi_device_id *id = NULL;
  1379. +- struct flash_info *info;
  1380. ++ const struct flash_info *info = NULL;
  1381. + struct device *dev = nor->dev;
  1382. +- struct mtd_info *mtd = nor->mtd;
  1383. +- struct device_node *np = dev->of_node;
  1384. ++ struct mtd_info *mtd = &nor->mtd;
  1385. ++ struct device_node *np = nor->flash_node;
  1386. + int ret;
  1387. + int i;
  1388. +
  1389. +@@ -926,19 +1115,25 @@ int spi_nor_scan(struct spi_nor *nor, co
  1390. + if (ret)
  1391. + return ret;
  1392. +
  1393. +- id = spi_nor_match_id(name);
  1394. +- if (!id)
  1395. ++ if (name)
  1396. ++ info = spi_nor_match_id(name);
  1397. ++ /* Try to auto-detect if chip name wasn't specified or not found */
  1398. ++ if (!info)
  1399. ++ info = spi_nor_read_id(nor);
  1400. ++ if (IS_ERR_OR_NULL(info))
  1401. + return -ENOENT;
  1402. +
  1403. +- info = (void *)id->driver_data;
  1404. +-
  1405. +- if (info->jedec_id) {
  1406. +- const struct spi_device_id *jid;
  1407. ++ /*
  1408. ++ * If caller has specified name of flash model that can normally be
  1409. ++ * detected using JEDEC, let's verify it.
  1410. ++ */
  1411. ++ if (name && info->id_len) {
  1412. ++ const struct flash_info *jinfo;
  1413. +
  1414. +- jid = nor->read_id(nor);
  1415. +- if (IS_ERR(jid)) {
  1416. +- return PTR_ERR(jid);
  1417. +- } else if (jid != id) {
  1418. ++ jinfo = spi_nor_read_id(nor);
  1419. ++ if (IS_ERR(jinfo)) {
  1420. ++ return PTR_ERR(jinfo);
  1421. ++ } else if (jinfo != info) {
  1422. + /*
  1423. + * JEDEC knows better, so overwrite platform ID. We
  1424. + * can't trust partitions any longer, but we'll let
  1425. +@@ -947,28 +1142,28 @@ int spi_nor_scan(struct spi_nor *nor, co
  1426. + * information, even if it's not 100% accurate.
  1427. + */
  1428. + dev_warn(dev, "found %s, expected %s\n",
  1429. +- jid->name, id->name);
  1430. +- id = jid;
  1431. +- info = (void *)jid->driver_data;
  1432. ++ jinfo->name, info->name);
  1433. ++ info = jinfo;
  1434. + }
  1435. + }
  1436. +
  1437. + mutex_init(&nor->lock);
  1438. +
  1439. + /*
  1440. +- * Atmel, SST and Intel/Numonyx serial nor tend to power
  1441. +- * up with the software protection bits set
  1442. ++ * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up
  1443. ++ * with the software protection bits set
  1444. + */
  1445. +
  1446. +- if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
  1447. +- JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
  1448. +- JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
  1449. ++ if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
  1450. ++ JEDEC_MFR(info) == SNOR_MFR_INTEL ||
  1451. ++ JEDEC_MFR(info) == SNOR_MFR_SST) {
  1452. + write_enable(nor);
  1453. + write_sr(nor, 0);
  1454. + }
  1455. +
  1456. + if (!mtd->name)
  1457. + mtd->name = dev_name(dev);
  1458. ++ mtd->priv = nor;
  1459. + mtd->type = MTD_NORFLASH;
  1460. + mtd->writesize = 1;
  1461. + mtd->flags = MTD_CAP_NORFLASH;
  1462. +@@ -976,10 +1171,17 @@ int spi_nor_scan(struct spi_nor *nor, co
  1463. + mtd->_erase = spi_nor_erase;
  1464. + mtd->_read = spi_nor_read;
  1465. +
  1466. +- /* nor protection support for STmicro chips */
  1467. +- if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
  1468. ++ /* NOR protection support for STmicro/Micron chips and similar */
  1469. ++ if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
  1470. ++ nor->flash_lock = stm_lock;
  1471. ++ nor->flash_unlock = stm_unlock;
  1472. ++ nor->flash_is_locked = stm_is_locked;
  1473. ++ }
  1474. ++
  1475. ++ if (nor->flash_lock && nor->flash_unlock && nor->flash_is_locked) {
  1476. + mtd->_lock = spi_nor_lock;
  1477. + mtd->_unlock = spi_nor_unlock;
  1478. ++ mtd->_is_locked = spi_nor_is_locked;
  1479. + }
  1480. +
  1481. + /* sst nor chips use AAI word program */
  1482. +@@ -988,9 +1190,8 @@ int spi_nor_scan(struct spi_nor *nor, co
  1483. + else
  1484. + mtd->_write = spi_nor_write;
  1485. +
  1486. +- if ((info->flags & USE_FSR) &&
  1487. +- nor->wait_till_ready == spi_nor_wait_till_ready)
  1488. +- nor->wait_till_ready = spi_nor_wait_till_fsr_ready;
  1489. ++ if (info->flags & USE_FSR)
  1490. ++ nor->flags |= SNOR_F_USE_FSR;
  1491. +
  1492. + #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
  1493. + /* prefer "small sector" erase if possible */
  1494. +@@ -1031,7 +1232,7 @@ int spi_nor_scan(struct spi_nor *nor, co
  1495. +
  1496. + /* Quad/Dual-read mode takes precedence over fast/normal */
  1497. + if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
  1498. +- ret = set_quad_mode(nor, info->jedec_id);
  1499. ++ ret = set_quad_mode(nor, info);
  1500. + if (ret) {
  1501. + dev_err(dev, "quad mode not supported\n");
  1502. + return ret;
  1503. +@@ -1067,7 +1268,7 @@ int spi_nor_scan(struct spi_nor *nor, co
  1504. + else if (mtd->size > 0x1000000) {
  1505. + /* enable 4-byte addressing if the device exceeds 16MiB */
  1506. + nor->addr_width = 4;
  1507. +- if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
  1508. ++ if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
  1509. + /* Dedicated 4-byte command set */
  1510. + switch (nor->flash_read) {
  1511. + case SPI_NOR_QUAD:
  1512. +@@ -1088,14 +1289,14 @@ int spi_nor_scan(struct spi_nor *nor, co
  1513. + nor->erase_opcode = SPINOR_OP_SE_4B;
  1514. + mtd->erasesize = info->sector_size;
  1515. + } else
  1516. +- set_4byte(nor, info->jedec_id, 1);
  1517. ++ set_4byte(nor, info, 1);
  1518. + } else {
  1519. + nor->addr_width = 3;
  1520. + }
  1521. +
  1522. + nor->read_dummy = spi_nor_read_dummy_cycles(nor);
  1523. +
  1524. +- dev_info(dev, "%s (%lld Kbytes)\n", id->name,
  1525. ++ dev_info(dev, "%s (%lld Kbytes)\n", info->name,
  1526. + (long long)mtd->size >> 10);
  1527. +
  1528. + dev_dbg(dev,
  1529. +@@ -1118,11 +1319,11 @@ int spi_nor_scan(struct spi_nor *nor, co
  1530. + }
  1531. + EXPORT_SYMBOL_GPL(spi_nor_scan);
  1532. +
  1533. +-static const struct spi_device_id *spi_nor_match_id(const char *name)
  1534. ++static const struct flash_info *spi_nor_match_id(const char *name)
  1535. + {
  1536. +- const struct spi_device_id *id = spi_nor_ids;
  1537. ++ const struct flash_info *id = spi_nor_ids;
  1538. +
  1539. +- while (id->name[0]) {
  1540. ++ while (id->name) {
  1541. + if (!strcmp(name, id->name))
  1542. + return id;
  1543. + id++;
  1544. +--- a/include/linux/mtd/spi-nor.h
  1545. ++++ b/include/linux/mtd/spi-nor.h
  1546. +@@ -10,6 +10,23 @@
  1547. + #ifndef __LINUX_MTD_SPI_NOR_H
  1548. + #define __LINUX_MTD_SPI_NOR_H
  1549. +
  1550. ++#include <linux/bitops.h>
  1551. ++#include <linux/mtd/cfi.h>
  1552. ++
  1553. ++/*
  1554. ++ * Manufacturer IDs
  1555. ++ *
  1556. ++ * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
  1557. ++ * Sometimes these are the same as CFI IDs, but sometimes they aren't.
  1558. ++ */
  1559. ++#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
  1560. ++#define SNOR_MFR_INTEL CFI_MFR_INTEL
  1561. ++#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
  1562. ++#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
  1563. ++#define SNOR_MFR_SPANSION CFI_MFR_AMD
  1564. ++#define SNOR_MFR_SST CFI_MFR_SST
  1565. ++#define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
  1566. ++
  1567. + /*
  1568. + * Note on opcode nomenclature: some opcodes have a format like
  1569. + * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
  1570. +@@ -56,22 +73,29 @@
  1571. + /* Used for Spansion flashes only. */
  1572. + #define SPINOR_OP_BRWR 0x17 /* Bank register write */
  1573. +
  1574. ++/* Used for Micron flashes only. */
  1575. ++#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
  1576. ++#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
  1577. ++
  1578. + /* Status Register bits. */
  1579. +-#define SR_WIP 1 /* Write in progress */
  1580. +-#define SR_WEL 2 /* Write enable latch */
  1581. ++#define SR_WIP BIT(0) /* Write in progress */
  1582. ++#define SR_WEL BIT(1) /* Write enable latch */
  1583. + /* meaning of other SR_* bits may differ between vendors */
  1584. +-#define SR_BP0 4 /* Block protect 0 */
  1585. +-#define SR_BP1 8 /* Block protect 1 */
  1586. +-#define SR_BP2 0x10 /* Block protect 2 */
  1587. +-#define SR_SRWD 0x80 /* SR write protect */
  1588. ++#define SR_BP0 BIT(2) /* Block protect 0 */
  1589. ++#define SR_BP1 BIT(3) /* Block protect 1 */
  1590. ++#define SR_BP2 BIT(4) /* Block protect 2 */
  1591. ++#define SR_SRWD BIT(7) /* SR write protect */
  1592. ++
  1593. ++#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
  1594. +
  1595. +-#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
  1596. ++/* Enhanced Volatile Configuration Register bits */
  1597. ++#define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
  1598. +
  1599. + /* Flag Status Register bits */
  1600. +-#define FSR_READY 0x80
  1601. ++#define FSR_READY BIT(7)
  1602. +
  1603. + /* Configuration Register bits. */
  1604. +-#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
  1605. ++#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
  1606. +
  1607. + enum read_mode {
  1608. + SPI_NOR_NORMAL = 0,
  1609. +@@ -80,33 +104,6 @@ enum read_mode {
  1610. + SPI_NOR_QUAD,
  1611. + };
  1612. +
  1613. +-/**
  1614. +- * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
  1615. +- * @wren: command for "Write Enable", or 0x00 for not required
  1616. +- * @cmd: command for operation
  1617. +- * @cmd_pins: number of pins to send @cmd (1, 2, 4)
  1618. +- * @addr: address for operation
  1619. +- * @addr_pins: number of pins to send @addr (1, 2, 4)
  1620. +- * @addr_width: number of address bytes
  1621. +- * (3,4, or 0 for address not required)
  1622. +- * @mode: mode data
  1623. +- * @mode_pins: number of pins to send @mode (1, 2, 4)
  1624. +- * @mode_cycles: number of mode cycles (0 for mode not required)
  1625. +- * @dummy_cycles: number of dummy cycles (0 for dummy not required)
  1626. +- */
  1627. +-struct spi_nor_xfer_cfg {
  1628. +- u8 wren;
  1629. +- u8 cmd;
  1630. +- u8 cmd_pins;
  1631. +- u32 addr;
  1632. +- u8 addr_pins;
  1633. +- u8 addr_width;
  1634. +- u8 mode;
  1635. +- u8 mode_pins;
  1636. +- u8 mode_cycles;
  1637. +- u8 dummy_cycles;
  1638. +-};
  1639. +-
  1640. + #define SPI_NOR_MAX_CMD_SIZE 8
  1641. + enum spi_nor_ops {
  1642. + SPI_NOR_OPS_READ = 0,
  1643. +@@ -116,11 +113,18 @@ enum spi_nor_ops {
  1644. + SPI_NOR_OPS_UNLOCK,
  1645. + };
  1646. +
  1647. ++enum spi_nor_option_flags {
  1648. ++ SNOR_F_USE_FSR = BIT(0),
  1649. ++};
  1650. ++
  1651. ++struct mtd_info;
  1652. ++
  1653. + /**
  1654. + * struct spi_nor - Structure for defining a the SPI NOR layer
  1655. + * @mtd: point to a mtd_info structure
  1656. + * @lock: the lock for the read/write/erase/lock/unlock operations
  1657. + * @dev: point to a spi device, or a spi nor controller device.
  1658. ++ * @flash_node: point to a device node describing this flash instance.
  1659. + * @page_size: the page size of the SPI NOR
  1660. + * @addr_width: number of address bytes
  1661. + * @erase_opcode: the opcode for erasing a sector
  1662. +@@ -129,29 +133,29 @@ enum spi_nor_ops {
  1663. + * @program_opcode: the program opcode
  1664. + * @flash_read: the mode of the read
  1665. + * @sst_write_second: used by the SST write operation
  1666. +- * @cfg: used by the read_xfer/write_xfer
  1667. ++ * @flags: flag options for the current SPI-NOR (SNOR_F_*)
  1668. + * @cmd_buf: used by the write_reg
  1669. + * @prepare: [OPTIONAL] do some preparations for the
  1670. + * read/write/erase/lock/unlock operations
  1671. + * @unprepare: [OPTIONAL] do some post work after the
  1672. + * read/write/erase/lock/unlock operations
  1673. +- * @read_xfer: [OPTIONAL] the read fundamental primitive
  1674. +- * @write_xfer: [OPTIONAL] the writefundamental primitive
  1675. + * @read_reg: [DRIVER-SPECIFIC] read out the register
  1676. + * @write_reg: [DRIVER-SPECIFIC] write data to the register
  1677. +- * @read_id: [REPLACEABLE] read out the ID data, and find
  1678. +- * the proper spi_device_id
  1679. +- * @wait_till_ready: [REPLACEABLE] wait till the NOR becomes ready
  1680. + * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
  1681. + * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
  1682. + * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
  1683. + * at the offset @offs
  1684. ++ * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
  1685. ++ * @flash_unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
  1686. ++ * @flash_is_locked: [FLASH-SPECIFIC] check if a region of the SPI NOR is
  1687. ++ * completely locked
  1688. + * @priv: the private data
  1689. + */
  1690. + struct spi_nor {
  1691. +- struct mtd_info *mtd;
  1692. ++ struct mtd_info mtd;
  1693. + struct mutex lock;
  1694. + struct device *dev;
  1695. ++ struct device_node *flash_node;
  1696. + u32 page_size;
  1697. + u8 addr_width;
  1698. + u8 erase_opcode;
  1699. +@@ -160,20 +164,13 @@ struct spi_nor {
  1700. + u8 program_opcode;
  1701. + enum read_mode flash_read;
  1702. + bool sst_write_second;
  1703. +- struct spi_nor_xfer_cfg cfg;
  1704. ++ u32 flags;
  1705. + u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
  1706. +
  1707. + int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
  1708. + void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
  1709. +- int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
  1710. +- u8 *buf, size_t len);
  1711. +- int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
  1712. +- u8 *buf, size_t len);
  1713. + int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
  1714. +- int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
  1715. +- int write_enable);
  1716. +- const struct spi_device_id *(*read_id)(struct spi_nor *nor);
  1717. +- int (*wait_till_ready)(struct spi_nor *nor);
  1718. ++ int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
  1719. +
  1720. + int (*read)(struct spi_nor *nor, loff_t from,
  1721. + size_t len, size_t *retlen, u_char *read_buf);
  1722. +@@ -181,6 +178,10 @@ struct spi_nor {
  1723. + size_t len, size_t *retlen, const u_char *write_buf);
  1724. + int (*erase)(struct spi_nor *nor, loff_t offs);
  1725. +
  1726. ++ int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  1727. ++ int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  1728. ++ int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
  1729. ++
  1730. + void *priv;
  1731. + };
  1732. +
  1733. diff --git a/target/linux/generic/patches-3.18/462-m25p80-mx-disable-software-protection.patch b/target/linux/generic/patches-3.18/462-m25p80-mx-disable-software-protection.patch
  1734. index fef483a..eb99609 100644
  1735. --- a/target/linux/generic/patches-3.18/462-m25p80-mx-disable-software-protection.patch
  1736. +++ b/target/linux/generic/patches-3.18/462-m25p80-mx-disable-software-protection.patch
  1737. @@ -1,10 +1,14 @@
  1738. +Disable software protection bits for Macronix flashes.
  1739. +
  1740. +Signed-off-by: Felix Fietkau <nbd@openwrt.org>
  1741. +
  1742. --- a/drivers/mtd/spi-nor/spi-nor.c
  1743. +++ b/drivers/mtd/spi-nor/spi-nor.c
  1744. -@@ -963,6 +963,7 @@ int spi_nor_scan(struct spi_nor *nor, co
  1745. +@@ -1164,6 +1164,7 @@ int spi_nor_scan(struct spi_nor *nor, co
  1746. - if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
  1747. - JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
  1748. -+ JEDEC_MFR(info->jedec_id) == CFI_MFR_MACRONIX ||
  1749. - JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
  1750. + if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
  1751. + JEDEC_MFR(info) == SNOR_MFR_INTEL ||
  1752. ++ JEDEC_MFR(info) == SNOR_MFR_MACRONIX ||
  1753. + JEDEC_MFR(info) == SNOR_MFR_SST) {
  1754. write_enable(nor);
  1755. write_sr(nor, 0);
  1756. diff --git a/target/linux/generic/patches-3.18/472-mtd-m25p80-add-support-for-Winbond-W25X05-flash.patch b/target/linux/generic/patches-3.18/472-mtd-m25p80-add-support-for-Winbond-W25X05-flash.patch
  1757. deleted file mode 100644
  1758. index dca6895..0000000
  1759. --- a/target/linux/generic/patches-3.18/472-mtd-m25p80-add-support-for-Winbond-W25X05-flash.patch
  1760. +++ /dev/null
  1761. @@ -1,20 +0,0 @@
  1762. -From eef9dfc4e821408af1af13aa0cc707fc496fb7c6 Mon Sep 17 00:00:00 2001
  1763. -From: Gabor Juhos <juhosg@openwrt.org>
  1764. -Date: Wed, 11 Dec 2013 19:05:59 +0100
  1765. -Subject: [PATCH] m25p80: add support for the Winbond W25X05 flash
  1766. -
  1767. -Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  1768. ----
  1769. - drivers/mtd/devices/m25p80.c | 1 +
  1770. - 1 file changed, 1 insertion(+)
  1771. -
  1772. ---- a/drivers/mtd/spi-nor/spi-nor.c
  1773. -+++ b/drivers/mtd/spi-nor/spi-nor.c
  1774. -@@ -617,6 +617,7 @@ static const struct spi_device_id spi_no
  1775. - { "m25px80", INFO(0x207114, 0, 64 * 1024, 16, 0) },
  1776. -
  1777. - /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
  1778. -+ { "w25x05", INFO(0xef3010, 0, 64 * 1024, 1, SECT_4K) },
  1779. - { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
  1780. - { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
  1781. - { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
  1782. diff --git a/target/linux/generic/patches-3.18/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch b/target/linux/generic/patches-3.18/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch
  1783. deleted file mode 100644
  1784. index 9ba7a4a..0000000
  1785. --- a/target/linux/generic/patches-3.18/473-mtd-spi-nor-add-support-for-the-Macronix-MX25L512E-S.patch
  1786. +++ /dev/null
  1787. @@ -1,21 +0,0 @@
  1788. -From 0d7388de0911c1a4fc4a8a3898ef9d0ab818ca08 Mon Sep 17 00:00:00 2001
  1789. -From: Gabor Juhos <juhosg@openwrt.org>
  1790. -Date: Tue, 7 Apr 2015 18:35:15 +0200
  1791. -Subject: [PATCH] mtd: spi-nor: add support for the Macronix MX25L512E SPI
  1792. - flash chip
  1793. -
  1794. -Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  1795. ----
  1796. - drivers/mtd/spi-nor/spi-nor.c | 1 +
  1797. - 1 file changed, 1 insertion(+)
  1798. -
  1799. ---- a/drivers/mtd/spi-nor/spi-nor.c
  1800. -+++ b/drivers/mtd/spi-nor/spi-nor.c
  1801. -@@ -518,6 +518,7 @@ static const struct spi_device_id spi_no
  1802. - { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
  1803. -
  1804. - /* Macronix */
  1805. -+ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
  1806. - { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
  1807. - { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
  1808. - { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
  1809. diff --git a/target/linux/generic/patches-3.18/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch b/target/linux/generic/patches-3.18/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch
  1810. deleted file mode 100644
  1811. index b06ac73..0000000
  1812. --- a/target/linux/generic/patches-3.18/474-mtd-spi-nor-add-support-for-the-ISSI-SI25CD512-SPI-f.patch
  1813. +++ /dev/null
  1814. @@ -1,22 +0,0 @@
  1815. -From 34e2b403040a2f9d3ba071d95a7f42457e2950f9 Mon Sep 17 00:00:00 2001
  1816. -From: Gabor Juhos <juhosg@openwrt.org>
  1817. -Date: Tue, 7 Apr 2015 18:35:15 +0200
  1818. -Subject: [PATCH] mtd: spi-nor: add support for the ISSI SI25CD512 SPI flash
  1819. -
  1820. -Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  1821. ----
  1822. - drivers/mtd/spi-nor/spi-nor.c | 3 +++
  1823. - 1 file changed, 3 insertions(+)
  1824. -
  1825. ---- a/drivers/mtd/spi-nor/spi-nor.c
  1826. -+++ b/drivers/mtd/spi-nor/spi-nor.c
  1827. -@@ -517,6 +517,9 @@ static const struct spi_device_id spi_no
  1828. - { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
  1829. - { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
  1830. -
  1831. -+ /* ISSI */
  1832. -+ { "is25cd512", INFO(0x7f9d20, 0, 32 * 1024, 2, SECT_4K) },
  1833. -+
  1834. - /* Macronix */
  1835. - { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
  1836. - { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
  1837. diff --git a/target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch b/target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch
  1838. deleted file mode 100644
  1839. index 203eb94..0000000
  1840. --- a/target/linux/lantiq/patches-3.18/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch
  1841. +++ /dev/null
  1842. @@ -1,44 +0,0 @@
  1843. -From 4400e1f593ea40a51912128adb4f53d59e62cad8 Mon Sep 17 00:00:00 2001
  1844. -From: John Crispin <blogic@openwrt.org>
  1845. -Date: Wed, 10 Sep 2014 22:40:18 +0200
  1846. -Subject: [PATCH 22/36] MTD: m25p80: allow loading mtd name from OF
  1847. -
  1848. -In accordance with the physmap flash we should honour the linux,mtd-name
  1849. -property when deciding what name the mtd device has.
  1850. -
  1851. -Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
  1852. -Signed-off-by: John Crispin <blogic@openwrt.org>
  1853. ----
  1854. - drivers/mtd/devices/m25p80.c | 6 ++++++
  1855. - 1 file changed, 6 insertions(+)
  1856. -
  1857. ---- a/drivers/mtd/devices/m25p80.c
  1858. -+++ b/drivers/mtd/devices/m25p80.c
  1859. -@@ -19,6 +19,7 @@
  1860. - #include <linux/errno.h>
  1861. - #include <linux/module.h>
  1862. - #include <linux/device.h>
  1863. -+#include <linux/of.h>
  1864. -
  1865. - #include <linux/mtd/mtd.h>
  1866. - #include <linux/mtd/partitions.h>
  1867. -@@ -198,6 +199,10 @@ static int m25p_probe(struct spi_device
  1868. - enum read_mode mode = SPI_NOR_NORMAL;
  1869. - char *flash_name = NULL;
  1870. - int ret;
  1871. -+ const char __maybe_unused *of_mtd_name = NULL;
  1872. -+
  1873. -+ of_property_read_string(spi->dev.of_node,
  1874. -+ "linux,mtd-name", &of_mtd_name);
  1875. -
  1876. - data = dev_get_platdata(&spi->dev);
  1877. -
  1878. -@@ -229,6 +234,8 @@ static int m25p_probe(struct spi_device
  1879. -
  1880. - if (data && data->name)
  1881. - flash->mtd.name = data->name;
  1882. -+ else if (of_mtd_name)
  1883. -+ flash->mtd.name = of_mtd_name;
  1884. -
  1885. - /* For some (historical?) reason many platforms provide two different
  1886. - * names in flash_platform_data: "name" and "type". Quite often name is
  1887. diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
  1888. index 2beb39c..21f823d 100644
  1889. --- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
  1890. +++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
  1891. @@ -37,7 +37,7 @@
  1892. flash@0 {
  1893. #address-cells = <1>;
  1894. #size-cells = <1>;
  1895. - compatible = "spansion,s25fl129p1";
  1896. + compatible = "jedec,spi-nor";
  1897. reg = <0>;
  1898. spi-max-frequency = <25000000>;
  1899. diff --git a/target/linux/ramips/patches-3.18/0044-mtd-add-chunked-read-io-to-m25p80.patch b/target/linux/ramips/patches-3.18/0044-mtd-add-chunked-read-io-to-m25p80.patch
  1900. index 1716e1c..8dc181a 100644
  1901. --- a/target/linux/ramips/patches-3.18/0044-mtd-add-chunked-read-io-to-m25p80.patch
  1902. +++ b/target/linux/ramips/patches-3.18/0044-mtd-add-chunked-read-io-to-m25p80.patch
  1903. @@ -1,33 +1,18 @@
  1904. ---- a/drivers/mtd/devices/m25p80.c
  1905. -+++ b/drivers/mtd/devices/m25p80.c
  1906. -@@ -19,6 +19,7 @@
  1907. - #include <linux/errno.h>
  1908. - #include <linux/module.h>
  1909. - #include <linux/device.h>
  1910. -+#include <linux/of.h>
  1911. -
  1912. - #include <linux/mtd/mtd.h>
  1913. - #include <linux/mtd/partitions.h>
  1914. -@@ -32,6 +33,7 @@ struct m25p {
  1915. - struct spi_device *spi;
  1916. - struct spi_nor spi_nor;
  1917. - struct mtd_info mtd;
  1918. -+ u16 chunk_size;
  1919. - u8 command[MAX_CMD_SIZE];
  1920. - };
  1921. -
  1922. -@@ -157,6 +159,61 @@ static int m25p80_read(struct spi_nor *n
  1923. - return 0;
  1924. +--- a/drivers/mtd/spi-nor/spi-nor.c
  1925. ++++ b/drivers/mtd/spi-nor/spi-nor.c
  1926. +@@ -1016,6 +1016,66 @@ write_err:
  1927. + return ret;
  1928. }
  1929. -+static void m25p80_chunked_write(struct spi_nor *nor, loff_t _from, size_t _len,
  1930. -+ size_t *_retlen, const u_char *_buf)
  1931. ++static int spi_nor_chunked_write(struct mtd_info *mtd, loff_t _to, size_t _len,
  1932. ++ size_t *_retlen, const u_char *_buf)
  1933. +{
  1934. -+ struct m25p *flash = nor->priv;
  1935. ++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1936. + int chunk_size;
  1937. + int retlen = 0;
  1938. ++ int ret;
  1939. +
  1940. -+ chunk_size = flash->chunk_size;
  1941. ++ chunk_size = nor->chunk_size;
  1942. + if (!chunk_size)
  1943. + chunk_size = _len;
  1944. +
  1945. @@ -37,35 +22,39 @@
  1946. + while (retlen < _len) {
  1947. + size_t len = min_t(int, chunk_size, _len - retlen);
  1948. + const u_char *buf = _buf + retlen;
  1949. -+ loff_t from = _from + retlen;
  1950. -+
  1951. -+ nor->wait_till_ready(nor);
  1952. -+ nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
  1953. ++ loff_t to = _to + retlen;
  1954. +
  1955. -+ m25p80_write(nor, from, len, &retlen, buf);
  1956. ++ if (nor->flags & SNOR_F_SST)
  1957. ++ ret = sst_write(mtd, to, len, &retlen, buf);
  1958. ++ else
  1959. ++ ret = spi_nor_write(mtd, to, len, &retlen, buf);
  1960. ++ if (ret)
  1961. ++ return ret;
  1962. + }
  1963. ++
  1964. + *_retlen += retlen;
  1965. ++ return 0;
  1966. +}
  1967. +
  1968. -+static int m25p80_chunked_read(struct spi_nor *nor, loff_t _from, size_t _len,
  1969. -+ size_t *_retlen, u_char *_buf)
  1970. ++static int spi_nor_chunked_read(struct mtd_info *mtd, loff_t _from, size_t _len,
  1971. ++ size_t *_retlen, u_char *_buf)
  1972. +{
  1973. -+ struct m25p *flash = nor->priv;
  1974. ++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
  1975. + int chunk_size;
  1976. ++ int ret;
  1977. +
  1978. -+ chunk_size = flash->chunk_size;
  1979. ++ chunk_size = nor->chunk_size;
  1980. + if (!chunk_size)
  1981. + chunk_size = _len;
  1982. +
  1983. + *_retlen = 0;
  1984. -+
  1985. + while (*_retlen < _len) {
  1986. + size_t len = min_t(int, chunk_size, _len - *_retlen);
  1987. + u_char *buf = _buf + *_retlen;
  1988. + loff_t from = _from + *_retlen;
  1989. + int retlen = 0;
  1990. -+ int ret = m25p80_read(nor, from, len, &retlen, buf);
  1991. +
  1992. ++ ret = spi_nor_read(mtd, from, len, &retlen, buf);
  1993. + if (ret)
  1994. + return ret;
  1995. +
  1996. @@ -75,29 +64,60 @@
  1997. + return 0;
  1998. +}
  1999. +
  2000. - static int m25p80_erase(struct spi_nor *nor, loff_t offset)
  2001. + static int macronix_quad_enable(struct spi_nor *nor)
  2002. {
  2003. - struct m25p *flash = nor->priv;
  2004. -@@ -197,6 +254,7 @@ static int m25p_probe(struct spi_device
  2005. - struct spi_nor *nor;
  2006. - enum read_mode mode = SPI_NOR_NORMAL;
  2007. - char *flash_name = NULL;
  2008. -+ u32 val;
  2009. - int ret;
  2010. -
  2011. - data = dev_get_platdata(&spi->dev);
  2012. -@@ -244,6 +302,14 @@ static int m25p_probe(struct spi_device
  2013. - if (ret)
  2014. - return ret;
  2015. + int ret, val;
  2016. +@@ -1197,10 +1257,12 @@ int spi_nor_scan(struct spi_nor *nor, co
  2017. + }
  2018. -+ if (spi->dev.of_node &&
  2019. -+ !of_property_read_u32(spi->dev.of_node, "m25p,chunked-io", &val)) {
  2020. -+ dev_warn(&spi->dev, "using chunked io\n");
  2021. -+ nor->read = m25p80_chunked_read;
  2022. -+ nor->write = m25p80_chunked_write;
  2023. -+ flash->chunk_size = val;
  2024. + /* sst nor chips use AAI word program */
  2025. +- if (info->flags & SST_WRITE)
  2026. ++ if (info->flags & SST_WRITE) {
  2027. + mtd->_write = sst_write;
  2028. +- else
  2029. ++ nor->flags |= SNOR_F_SST;
  2030. ++ } else {
  2031. + mtd->_write = spi_nor_write;
  2032. + }
  2033. +
  2034. + if (info->flags & USE_FSR)
  2035. + nor->flags |= SNOR_F_USE_FSR;
  2036. +@@ -1228,11 +1290,20 @@ int spi_nor_scan(struct spi_nor *nor, co
  2037. + mtd->writebufsize = nor->page_size;
  2038. +
  2039. + if (np) {
  2040. ++ u32 val;
  2041. +
  2042. - ppdata.of_node = spi->dev.of_node;
  2043. + /* If we were instantiated by DT, use it */
  2044. + if (of_property_read_bool(np, "m25p,fast-read"))
  2045. + nor->flash_read = SPI_NOR_FAST;
  2046. + else
  2047. + nor->flash_read = SPI_NOR_NORMAL;
  2048. ++
  2049. ++ if (!of_property_read_u32(np, "m25p,chunked-io", &val)) {
  2050. ++ dev_info(dev, "using chunked io (size=%d)\n", val);
  2051. ++ mtd->_read = spi_nor_chunked_read;
  2052. ++ mtd->_write = spi_nor_chunked_write;
  2053. ++ nor->chunk_size = val;
  2054. ++ }
  2055. + } else {
  2056. + /* If we weren't instantiated by DT, default to fast-read */
  2057. + nor->flash_read = SPI_NOR_FAST;
  2058. +--- a/include/linux/mtd/spi-nor.h
  2059. ++++ b/include/linux/mtd/spi-nor.h
  2060. +@@ -115,6 +115,7 @@ enum spi_nor_ops {
  2061. +
  2062. + enum spi_nor_option_flags {
  2063. + SNOR_F_USE_FSR = BIT(0),
  2064. ++ SNOR_F_SST = BIT(1),
  2065. + };
  2066. - return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
  2067. + struct mtd_info;
  2068. +@@ -157,6 +158,7 @@ struct spi_nor {
  2069. + struct device *dev;
  2070. + struct device_node *flash_node;
  2071. + u32 page_size;
  2072. ++ u16 chunk_size;
  2073. + u8 addr_width;
  2074. + u8 erase_opcode;
  2075. + u8 read_opcode;