0043-ar71xx-QCA956X-add-missing-register.patch 6.5 KB

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  1. From: Henryk Heisig <hyniu@o2.pl>
  2. Date: Fri, 6 Jan 2017 21:21:11 +0100
  3. Subject: ar71xx: QCA956X: add missing register
  4. Signed-off-by: Henryk Heisig <hyniu@o2.pl>
  5. diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  6. index 790c2d3396ffd0a0d00d13403b7f22e32863eef4..a8b19b68b2a46545fdd3ed6bdf14006f8a741185 100644
  7. --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  8. +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  9. @@ -686,7 +686,6 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
  10. case ATH79_SOC_AR7241:
  11. case ATH79_SOC_AR9330:
  12. case ATH79_SOC_AR9331:
  13. - case ATH79_SOC_QCA956X:
  14. case ATH79_SOC_TP9343:
  15. pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
  16. break;
  17. @@ -698,6 +697,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
  18. case ATH79_SOC_AR9342:
  19. case ATH79_SOC_AR9344:
  20. case ATH79_SOC_QCA9533:
  21. + case ATH79_SOC_QCA956X:
  22. switch (pdata->phy_if_mode) {
  23. case PHY_INTERFACE_MODE_MII:
  24. case PHY_INTERFACE_MODE_GMII:
  25. @@ -814,6 +814,27 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask)
  26. iounmap(base);
  27. }
  28. +void __init ath79_setup_qca956x_eth_cfg(u32 mask)
  29. +{
  30. + void __iomem *base;
  31. + u32 t;
  32. +
  33. + base = ioremap(QCA956X_GMAC_BASE, QCA956X_GMAC_SIZE);
  34. +
  35. + t = __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
  36. +
  37. + t &= ~(QCA956X_ETH_CFG_SW_ONLY_MODE |
  38. + QCA956X_ETH_CFG_SW_PHY_SWAP);
  39. +
  40. + t |= mask;
  41. +
  42. + __raw_writel(t, base + QCA956X_GMAC_REG_ETH_CFG);
  43. + /* flush write */
  44. + __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
  45. +
  46. + iounmap(base);
  47. +}
  48. +
  49. static int ath79_eth_instance __initdata;
  50. void __init ath79_register_eth(unsigned int id)
  51. {
  52. diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h
  53. index 5a226e40284b6853b59812ffc791e0612c91fa9b..fb9e4f63c66ef9008e423007ecff02c93c321fb8 100644
  54. --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h
  55. +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.h
  56. @@ -49,5 +49,6 @@ void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
  57. void ath79_setup_ar934x_eth_cfg(u32 mask);
  58. void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
  59. void ath79_setup_qca955x_eth_cfg(u32 mask);
  60. +void ath79_setup_qca956x_eth_cfg(u32 mask);
  61. #endif /* _ATH79_DEV_ETH_H */
  62. diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
  63. index 5fd352c638a75063945adadb64b1043cd81b506c..078fa157f242ce4350185d97a61ef5d1f3f16fc5 100644
  64. --- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
  65. +++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
  66. @@ -37,11 +37,13 @@ struct ag71xx_platform_data {
  67. u8 is_ar724x:1;
  68. u8 has_ar8216:1;
  69. u8 use_flow_control:1;
  70. + u8 is_qca956x:1;
  71. struct ag71xx_switch_platform_data *switch_data;
  72. void (*ddr_flush)(void);
  73. void (*set_speed)(int speed);
  74. + void (*update_pll)(u32 pll_10, u32 pll_100, u32 pll_1000);
  75. u32 fifo_cfg1;
  76. u32 fifo_cfg2;
  77. diff --git a/target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch
  78. new file mode 100644
  79. index 0000000000000000000000000000000000000000..dff354398cd2ab6556b13be9f7ce45f4d7f311e8
  80. --- /dev/null
  81. +++ b/target/linux/ar71xx/patches-4.4/622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch
  82. @@ -0,0 +1,38 @@
  83. +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  84. ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  85. +@@ -157,6 +157,10 @@
  86. + #define QCA956X_EHCI0_BASE 0x1b000000
  87. + #define QCA956X_EHCI1_BASE 0x1b400000
  88. + #define QCA956X_EHCI_SIZE 0x200
  89. ++#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
  90. ++#define QCA956X_GMAC_SGMII_SIZE 0x64
  91. ++#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
  92. ++#define QCA956X_PLL_SIZE 0x50
  93. + #define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
  94. + #define QCA956X_GMAC_SIZE 0x64
  95. +
  96. +@@ -404,6 +408,7 @@
  97. + #define QCA956X_PLL_DDR_CONFIG_REG 0x08
  98. + #define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
  99. + #define QCA956X_PLL_CLK_CTRL_REG 0x10
  100. ++#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
  101. +
  102. + #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
  103. + #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
  104. +@@ -1186,4 +1191,16 @@
  105. + #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
  106. + #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
  107. +
  108. ++/*
  109. ++ * QCA956X GMAC Interface
  110. ++ */
  111. ++
  112. ++#define QCA956X_GMAC_REG_ETH_CFG 0x00
  113. ++
  114. ++#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
  115. ++#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
  116. ++#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
  117. ++#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
  118. ++#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
  119. ++
  120. + #endif /* __ASM_MACH_AR71XX_REGS_H */
  121. diff --git a/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch b/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
  122. index add2992186ad1d82ce924d2f1ccdf3c36c390a3d..8aa5957a7152af27854f6f7c197120b8029cf9e8 100644
  123. --- a/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
  124. +++ b/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
  125. @@ -20,7 +20,7 @@
  126. #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
  127. #define AR71XX_UART_SIZE 0x100
  128. #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
  129. -@@ -218,6 +218,9 @@
  130. +@@ -222,6 +222,9 @@
  131. #define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
  132. #define QCA953X_DDR_REG_FLUSH_WMAC 0xac
  133. diff --git a/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch b/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch
  134. index 7db6ad361fa21252118e589195b0bc73222cf4f5..6b331587d157511a40fc1e46630c416a60565a0b 100644
  135. --- a/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch
  136. +++ b/target/linux/ar71xx/patches-4.4/820-MIPS-ath79-add_gpio_function2_setup.patch
  137. @@ -48,7 +48,7 @@ functions on the Arduino Yun.
  138. void __iomem *reg = ath79_gpio_get_function_reg();
  139. --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  140. +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  141. -@@ -850,6 +850,7 @@
  142. +@@ -855,6 +855,7 @@
  143. #define AR71XX_GPIO_REG_INT_PENDING 0x20
  144. #define AR71XX_GPIO_REG_INT_ENABLE 0x24
  145. #define AR71XX_GPIO_REG_FUNC 0x28
  146. @@ -56,7 +56,7 @@ functions on the Arduino Yun.
  147. #define AR934X_GPIO_REG_OUT_FUNC0 0x2c
  148. #define AR934X_GPIO_REG_OUT_FUNC1 0x30
  149. -@@ -974,6 +975,8 @@
  150. +@@ -979,6 +980,8 @@
  151. #define AR724X_GPIO_FUNC_UART_EN BIT(1)
  152. #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)