0053-ar71xx-Extend-the-list-of-bits-in-QCA955X_GMAC_REG_ETH_CFG.patch 1.8 KB

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  1. From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
  2. Date: Wed, 16 Mar 2016 09:27:01 +0000
  3. Subject: ar71xx: Extend the list of bits in QCA955X_GMAC_REG_ETH_CFG
  4. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
  5. Backport of r49027
  6. Forwarded: https://patchwork.ozlabs.org/patch/624180/
  7. diff --git a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
  8. index 8bf7658..797977f 100644
  9. --- a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
  10. +++ b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
  11. @@ -207,7 +207,7 @@
  12. #define AR934X_GPIO_REG_FUNC 0x6c
  13. #define AR71XX_GPIO_COUNT 16
  14. -@@ -560,4 +663,153 @@
  15. +@@ -560,4 +663,170 @@
  16. #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
  17. #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
  18. @@ -358,6 +358,23 @@
  19. +#define QCA955X_GMAC_REG_ETH_CFG 0x00
  20. +
  21. +#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
  22. ++#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
  23. ++#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
  24. ++#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
  25. ++#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
  26. ++#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
  27. +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
  28. ++#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
  29. ++#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
  30. ++#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
  31. ++#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
  32. ++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
  33. ++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
  34. ++#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
  35. ++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
  36. ++#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
  37. ++#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
  38. ++#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
  39. ++#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
  40. +
  41. #endif /* __ASM_MACH_AR71XX_REGS_H */