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- From: Matthias Schiffer <mschiffer@universe-factory.net>
- Date: Fri, 13 May 2016 22:58:50 +0200
- Subject: ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
- Incorrect value causes clock inaccuracy as huge as 1/60.
- Signed-off-by: Dmitry Ivanov <dima@ubnt.com>
- Signed-off-by: Felix Fietkau <nbd@openwrt.org>
- Backport of OpenWrt r47363
- diff --git a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
- index b5c88e9..d3a14b2 100644
- --- a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
- +++ b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
- @@ -529,7 +529,7 @@
- +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
- +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
- +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
- -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff
- ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
- +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
- +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
- +
- @@ -541,7 +541,7 @@
- +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
- +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
- +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
- -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff
- ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
- +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
- +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
- +
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