0006-ar71xx-define-wmac-reset-function-for-QCA955x.patch 2.4 KB

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  1. From: Matthias Schiffer <mschiffer@universe-factory.net>
  2. Date: Tue, 19 Jul 2016 17:48:53 +0200
  3. Subject: ar71xx: define wmac reset function for QCA955x
  4. Signed-off-by: Felix Fietkau <nbd@nbd.name>
  5. Backport of LEDE a176168a85477caa44eef7e979567d1d52868fde
  6. diff --git a/target/linux/ar71xx/patches-3.18/640-MIPS-ath79-add-QCA955x-wmac-reset.patch b/target/linux/ar71xx/patches-3.18/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
  7. new file mode 100644
  8. index 0000000..4ac5acd
  9. --- /dev/null
  10. +++ b/target/linux/ar71xx/patches-3.18/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
  11. @@ -0,0 +1,71 @@
  12. +--- a/arch/mips/ath79/common.h
  13. ++++ b/arch/mips/ath79/common.h
  14. +@@ -19,6 +19,8 @@
  15. + #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
  16. + #define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
  17. +
  18. ++extern void __iomem *ath79_ddr_base;
  19. ++
  20. + void ath79_clocks_init(void);
  21. + unsigned long ath79_get_sys_clk_rate(const char *id);
  22. +
  23. +--- a/arch/mips/ath79/dev-wmac.c
  24. ++++ b/arch/mips/ath79/dev-wmac.c
  25. +@@ -149,6 +149,27 @@ static void ar934x_wmac_setup(void)
  26. + ath79_wmac_data.is_clk_25mhz = true;
  27. + }
  28. +
  29. ++static int ar955x_wmac_reset(void)
  30. ++{
  31. ++ int i;
  32. ++
  33. ++ /* Try to wait for WMAC DDR activity to stop */
  34. ++ for (i = 0; i < 10; i++) {
  35. ++ if (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) &
  36. ++ QCA955X_DDR_CTL_CONFIG_ACT_WMAC))
  37. ++ break;
  38. ++
  39. ++ udelay(10);
  40. ++ }
  41. ++
  42. ++ ath79_device_reset_set(QCA955X_RESET_RTC);
  43. ++ udelay(10);
  44. ++ ath79_device_reset_clear(QCA955X_RESET_RTC);
  45. ++ udelay(10);
  46. ++
  47. ++ return 0;
  48. ++}
  49. ++
  50. + static void qca955x_wmac_setup(void)
  51. + {
  52. + u32 t;
  53. +@@ -165,6 +186,8 @@ static void qca955x_wmac_setup(void)
  54. + ath79_wmac_data.is_clk_25mhz = false;
  55. + else
  56. + ath79_wmac_data.is_clk_25mhz = true;
  57. ++
  58. ++ ath79_wmac_data.external_reset = ar955x_wmac_reset;
  59. + }
  60. +
  61. + static bool __init
  62. +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  63. ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  64. +@@ -32,7 +32,7 @@
  65. + #define AR71XX_SPI_SIZE 0x01000000
  66. +
  67. + #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
  68. +-#define AR71XX_DDR_CTRL_SIZE 0x100
  69. ++#define AR71XX_DDR_CTRL_SIZE 0x200
  70. + #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
  71. + #define AR71XX_UART_SIZE 0x100
  72. + #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
  73. +@@ -173,6 +173,9 @@
  74. + #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
  75. + #define AR934X_DDR_REG_FLUSH_WMAC 0xac
  76. +
  77. ++#define QCA955X_DDR_CTL_CONFIG 0x108
  78. ++#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23)
  79. ++
  80. + /*
  81. + * PLL block
  82. + */