0017-ar71xx-add-support-for-QCA953x-SoC.patch 18 KB

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  1. From: Matthias Schiffer <mschiffer@universe-factory.net>
  2. Date: Sat, 29 Mar 2014 21:55:41 +0100
  3. Subject: ar71xx: add support for QCA953x SoC
  4. diff --git a/target/linux/ar71xx/config-3.3 b/target/linux/ar71xx/config-3.3
  5. index dfc5bf2..1c3ba3c 100644
  6. --- a/target/linux/ar71xx/config-3.3
  7. +++ b/target/linux/ar71xx/config-3.3
  8. @@ -40,11 +40,11 @@ CONFIG_ATH79_MACH_EW_DORIN=y
  9. CONFIG_ATH79_MACH_HORNET_UB=y
  10. CONFIG_ATH79_MACH_JA76PF=y
  11. CONFIG_ATH79_MACH_JWAP003=y
  12. +CONFIG_ATH79_MACH_MR600=y
  13. CONFIG_ATH79_MACH_MZK_W04NU=y
  14. CONFIG_ATH79_MACH_MZK_W300NH=y
  15. CONFIG_ATH79_MACH_NBG460N=y
  16. CONFIG_ATH79_MACH_OM2P=y
  17. -CONFIG_ATH79_MACH_MR600=y
  18. CONFIG_ATH79_MACH_PB42=y
  19. CONFIG_ATH79_MACH_PB44=y
  20. CONFIG_ATH79_MACH_PB92=y
  21. @@ -214,6 +214,7 @@ CONFIG_SOC_AR724X=y
  22. CONFIG_SOC_AR913X=y
  23. CONFIG_SOC_AR933X=y
  24. CONFIG_SOC_AR934X=y
  25. +CONFIG_SOC_QCA953X=y
  26. CONFIG_SOC_QCA955X=y
  27. CONFIG_SPI=y
  28. CONFIG_SPI_AP83=y
  29. diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  30. index 5a0b950..1a9b0df 100644
  31. --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  32. +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  33. @@ -195,6 +195,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
  34. case ATH79_SOC_AR7241:
  35. case ATH79_SOC_AR9330:
  36. case ATH79_SOC_AR9331:
  37. + case ATH79_SOC_QCA9533:
  38. mdio_dev = &ath79_mdio1_device;
  39. mdio_data = &ath79_mdio1_data;
  40. break;
  41. @@ -250,6 +251,11 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
  42. }
  43. mdio_data->is_ar934x = 1;
  44. break;
  45. +
  46. + case ATH79_SOC_QCA9533:
  47. + mdio_data->builtin_switch = 1;
  48. + break;
  49. +
  50. case ATH79_SOC_QCA9558:
  51. if (id == 1)
  52. mdio_data->builtin_switch = 1;
  53. @@ -540,6 +546,7 @@ static void __init ath79_init_eth_pll_data(unsigned int id)
  54. case ATH79_SOC_AR9341:
  55. case ATH79_SOC_AR9342:
  56. case ATH79_SOC_AR9344:
  57. + case ATH79_SOC_QCA9533:
  58. case ATH79_SOC_QCA9558:
  59. pll_10 = AR934X_PLL_VAL_10;
  60. pll_100 = AR934X_PLL_VAL_100;
  61. @@ -596,6 +603,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
  62. case ATH79_SOC_AR7241:
  63. case ATH79_SOC_AR9330:
  64. case ATH79_SOC_AR9331:
  65. + case ATH79_SOC_QCA9533:
  66. pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
  67. break;
  68. @@ -645,6 +653,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
  69. case ATH79_SOC_AR7241:
  70. case ATH79_SOC_AR9330:
  71. case ATH79_SOC_AR9331:
  72. + case ATH79_SOC_QCA9533:
  73. pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
  74. break;
  75. @@ -882,6 +891,37 @@ void __init ath79_register_eth(unsigned int id)
  76. pdata->fifo_cfg3 = 0x01f00140;
  77. break;
  78. + case ATH79_SOC_QCA9533:
  79. + if (id == 0) {
  80. + pdata->reset_bit = AR933X_RESET_GE0_MAC |
  81. + AR933X_RESET_GE0_MDIO;
  82. + pdata->set_speed = ath79_set_speed_dummy;
  83. +
  84. + pdata->phy_mask = BIT(4);
  85. + } else {
  86. + pdata->reset_bit = AR933X_RESET_GE1_MAC |
  87. + AR933X_RESET_GE1_MDIO;
  88. + pdata->set_speed = ath79_set_speed_dummy;
  89. +
  90. + pdata->speed = SPEED_1000;
  91. + pdata->duplex = DUPLEX_FULL;
  92. + pdata->switch_data = &ath79_switch_data;
  93. +
  94. + ath79_switch_data.phy_poll_mask |= BIT(4);
  95. + }
  96. +
  97. + pdata->ddr_flush = ath79_ddr_no_flush;
  98. + pdata->has_gbit = 1;
  99. + pdata->is_ar724x = 1;
  100. +
  101. + if (!pdata->fifo_cfg1)
  102. + pdata->fifo_cfg1 = 0x0010ffff;
  103. + if (!pdata->fifo_cfg2)
  104. + pdata->fifo_cfg2 = 0x015500aa;
  105. + if (!pdata->fifo_cfg3)
  106. + pdata->fifo_cfg3 = 0x01f00140;
  107. + break;
  108. +
  109. case ATH79_SOC_AR9341:
  110. case ATH79_SOC_AR9342:
  111. case ATH79_SOC_AR9344:
  112. @@ -953,6 +993,7 @@ void __init ath79_register_eth(unsigned int id)
  113. case ATH79_SOC_AR7241:
  114. case ATH79_SOC_AR9330:
  115. case ATH79_SOC_AR9331:
  116. + case ATH79_SOC_QCA9533:
  117. pdata->mii_bus_dev = &ath79_mdio1_device.dev;
  118. break;
  119. diff --git a/target/linux/ar71xx/patches-3.3/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.3/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
  120. new file mode 100644
  121. index 0000000..4c9e761
  122. --- /dev/null
  123. +++ b/target/linux/ar71xx/patches-3.3/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
  124. @@ -0,0 +1,417 @@
  125. +From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
  126. +Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
  127. +From: Matthias Schiffer <mschiffer@universe-factory.net>
  128. +Date: Sat, 29 Mar 2014 20:26:08 +0100
  129. +Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
  130. +
  131. +Note that the clock calculation looks very similar to the QCA955x, but actually
  132. +some bits' meanings are slightly different.
  133. +---
  134. + arch/mips/ath79/Kconfig | 6 +-
  135. + arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++
  136. + arch/mips/ath79/common.c | 4 ++
  137. + arch/mips/ath79/dev-common.c | 1 +
  138. + arch/mips/ath79/dev-wmac.c | 20 +++++++
  139. + arch/mips/ath79/early_printk.c | 1 +
  140. + arch/mips/ath79/gpio.c | 4 +-
  141. + arch/mips/ath79/irq.c | 4 ++
  142. + arch/mips/ath79/setup.c | 8 ++-
  143. + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
  144. + arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
  145. + 11 files changed, 182 insertions(+), 3 deletions(-)
  146. +
  147. +--- a/arch/mips/ath79/Kconfig
  148. ++++ b/arch/mips/ath79/Kconfig
  149. +@@ -688,6 +688,10 @@ config SOC_AR934X
  150. + select PCI_AR724X if PCI
  151. + def_bool n
  152. +
  153. ++config SOC_QCA953X
  154. ++ select USB_ARCH_HAS_EHCI
  155. ++ def_bool n
  156. ++
  157. + config SOC_QCA955X
  158. + select USB_ARCH_HAS_EHCI
  159. + select HW_HAS_PCI
  160. +@@ -731,7 +735,7 @@ config ATH79_DEV_USB
  161. + def_bool n
  162. +
  163. + config ATH79_DEV_WMAC
  164. +- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
  165. ++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  166. + def_bool n
  167. +
  168. + config ATH79_NVRAM
  169. +--- a/arch/mips/ath79/clock.c
  170. ++++ b/arch/mips/ath79/clock.c
  171. +@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
  172. + iounmap(dpll_base);
  173. + }
  174. +
  175. ++static void __init qca953x_clocks_init(void)
  176. ++{
  177. ++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  178. ++ u32 cpu_pll, ddr_pll;
  179. ++ u32 bootstrap;
  180. ++
  181. ++ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  182. ++ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
  183. ++ ath79_ref_clk.rate = 40 * 1000 * 1000;
  184. ++ else
  185. ++ ath79_ref_clk.rate = 25 * 1000 * 1000;
  186. ++
  187. ++ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
  188. ++ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  189. ++ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
  190. ++ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  191. ++ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
  192. ++ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
  193. ++ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
  194. ++ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  195. ++ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
  196. ++
  197. ++ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
  198. ++ cpu_pll += frac * (ath79_ref_clk.rate >> 6) / ref_div;
  199. ++ cpu_pll /= (1 << out_div);
  200. ++
  201. ++ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
  202. ++ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  203. ++ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  204. ++ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  205. ++ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  206. ++ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
  207. ++ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  208. ++ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  209. ++ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
  210. ++
  211. ++ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
  212. ++ ddr_pll += frac * (ath79_ref_clk.rate >> 6) / (ref_div << 4);
  213. ++ ddr_pll /= (1 << out_div);
  214. ++
  215. ++ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
  216. ++
  217. ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  218. ++ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  219. ++
  220. ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  221. ++ ath79_cpu_clk.rate = ath79_ref_clk.rate;
  222. ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
  223. ++ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
  224. ++ else
  225. ++ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
  226. ++
  227. ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
  228. ++ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
  229. ++
  230. ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
  231. ++ ath79_ddr_clk.rate = ath79_ref_clk.rate;
  232. ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
  233. ++ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
  234. ++ else
  235. ++ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
  236. ++
  237. ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
  238. ++ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
  239. ++
  240. ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
  241. ++ ath79_ahb_clk.rate = ath79_ref_clk.rate;
  242. ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
  243. ++ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
  244. ++ else
  245. ++ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
  246. ++
  247. ++ ath79_wdt_clk.rate = ath79_ref_clk.rate;
  248. ++ ath79_uart_clk.rate = ath79_ref_clk.rate;
  249. ++}
  250. ++
  251. + static void __init qca955x_clocks_init(void)
  252. + {
  253. + u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  254. +@@ -383,6 +459,8 @@ void __init ath79_clocks_init(void)
  255. + ar933x_clocks_init();
  256. + else if (soc_is_ar934x())
  257. + ar934x_clocks_init();
  258. ++ else if (soc_is_qca953x())
  259. ++ qca953x_clocks_init();
  260. + else if (soc_is_qca955x())
  261. + qca955x_clocks_init();
  262. + else
  263. +--- a/arch/mips/ath79/common.c
  264. ++++ b/arch/mips/ath79/common.c
  265. +@@ -74,6 +74,8 @@ void ath79_device_reset_set(u32 mask)
  266. + else if (soc_is_ar934x() ||
  267. + soc_is_qca955x())
  268. + reg = AR934X_RESET_REG_RESET_MODULE;
  269. ++ else if (soc_is_qca953x())
  270. ++ reg = QCA953X_RESET_REG_RESET_MODULE;
  271. + else
  272. + BUG();
  273. +
  274. +@@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
  275. + else if (soc_is_ar934x() ||
  276. + soc_is_qca955x())
  277. + reg = AR934X_RESET_REG_RESET_MODULE;
  278. ++ else if (soc_is_qca953x())
  279. ++ reg = QCA953X_RESET_REG_RESET_MODULE;
  280. + else
  281. + BUG();
  282. +
  283. +--- a/arch/mips/ath79/dev-common.c
  284. ++++ b/arch/mips/ath79/dev-common.c
  285. +@@ -100,6 +100,7 @@ void __init ath79_register_uart(void)
  286. + soc_is_ar724x() ||
  287. + soc_is_ar913x() ||
  288. + soc_is_ar934x() ||
  289. ++ soc_is_qca953x() ||
  290. + soc_is_qca955x()) {
  291. + ath79_uart_data[0].uartclk = clk_get_rate(clk);
  292. + platform_device_register(&ath79_uart_device);
  293. +--- a/arch/mips/ath79/dev-wmac.c
  294. ++++ b/arch/mips/ath79/dev-wmac.c
  295. +@@ -99,7 +99,7 @@ static int ar933x_wmac_reset(void)
  296. + return -ETIMEDOUT;
  297. + }
  298. +
  299. +-static int ar933x_r1_get_wmac_revision(void)
  300. ++static int ar93xx_get_soc_revision(void)
  301. + {
  302. + return ath79_soc_rev;
  303. + }
  304. +@@ -124,7 +124,7 @@ static void __init ar933x_wmac_setup(voi
  305. + ath79_wmac_data.is_clk_25mhz = true;
  306. +
  307. + if (ath79_soc_rev == 1)
  308. +- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
  309. ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
  310. +
  311. + ath79_wmac_data.external_reset = ar933x_wmac_reset;
  312. + }
  313. +@@ -147,6 +147,26 @@ static void ar934x_wmac_setup(void)
  314. + ath79_wmac_data.is_clk_25mhz = true;
  315. + }
  316. +
  317. ++static void qca953x_wmac_setup(void)
  318. ++{
  319. ++ u32 t;
  320. ++
  321. ++ ath79_wmac_device.name = "qca953x_wmac";
  322. ++
  323. ++ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
  324. ++ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
  325. ++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
  326. ++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
  327. ++
  328. ++ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  329. ++ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
  330. ++ ath79_wmac_data.is_clk_25mhz = false;
  331. ++ else
  332. ++ ath79_wmac_data.is_clk_25mhz = true;
  333. ++
  334. ++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
  335. ++}
  336. ++
  337. + static void qca955x_wmac_setup(void)
  338. + {
  339. + u32 t;
  340. +@@ -314,6 +334,8 @@ void __init ath79_register_wmac(u8 *cal_
  341. + ar933x_wmac_setup();
  342. + else if (soc_is_ar934x())
  343. + ar934x_wmac_setup();
  344. ++ else if (soc_is_qca953x())
  345. ++ qca953x_wmac_setup();
  346. + else if (soc_is_qca955x())
  347. + qca955x_wmac_setup();
  348. + else
  349. +--- a/arch/mips/ath79/early_printk.c
  350. ++++ b/arch/mips/ath79/early_printk.c
  351. +@@ -114,6 +114,7 @@ static void prom_putchar_init(void)
  352. + case REV_ID_MAJOR_AR9341:
  353. + case REV_ID_MAJOR_AR9342:
  354. + case REV_ID_MAJOR_AR9344:
  355. ++ case REV_ID_MAJOR_QCA9533:
  356. + case REV_ID_MAJOR_QCA9558:
  357. + _prom_putchar = prom_putchar_ar71xx;
  358. + break;
  359. +--- a/arch/mips/ath79/gpio.c
  360. ++++ b/arch/mips/ath79/gpio.c
  361. +@@ -240,6 +240,8 @@ void __init ath79_gpio_init(void)
  362. + ath79_gpio_count = AR933X_GPIO_COUNT;
  363. + else if (soc_is_ar934x())
  364. + ath79_gpio_count = AR934X_GPIO_COUNT;
  365. ++ else if (soc_is_qca953x())
  366. ++ ath79_gpio_count = QCA953X_GPIO_COUNT;
  367. + else if (soc_is_qca955x())
  368. + ath79_gpio_count = QCA955X_GPIO_COUNT;
  369. + else
  370. +@@ -247,7 +249,7 @@ void __init ath79_gpio_init(void)
  371. +
  372. + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
  373. + ath79_gpio_chip.ngpio = ath79_gpio_count;
  374. +- if (soc_is_ar934x() || soc_is_qca955x()) {
  375. ++ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
  376. + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
  377. + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
  378. + }
  379. +--- a/arch/mips/ath79/irq.c
  380. ++++ b/arch/mips/ath79/irq.c
  381. +@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
  382. + else if (soc_is_ar724x() ||
  383. + soc_is_ar933x() ||
  384. + soc_is_ar934x() ||
  385. ++ soc_is_qca953x() ||
  386. + soc_is_qca955x())
  387. + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
  388. + else
  389. +@@ -352,6 +353,9 @@ void __init arch_init_irq(void)
  390. + } else if (soc_is_ar934x()) {
  391. + ath79_ip2_handler = ath79_default_ip2_handler;
  392. + ath79_ip3_handler = ar934x_ip3_handler;
  393. ++ } else if (soc_is_qca953x()) {
  394. ++ ath79_ip2_handler = ath79_default_ip2_handler;
  395. ++ ath79_ip3_handler = ath79_default_ip3_handler;
  396. + } else if (soc_is_qca955x()) {
  397. + ath79_ip2_handler = ath79_default_ip2_handler;
  398. + ath79_ip3_handler = ath79_default_ip3_handler;
  399. +--- a/arch/mips/ath79/setup.c
  400. ++++ b/arch/mips/ath79/setup.c
  401. +@@ -164,6 +164,12 @@ static void __init ath79_detect_sys_type
  402. + rev = id & AR934X_REV_ID_REVISION_MASK;
  403. + break;
  404. +
  405. ++ case REV_ID_MAJOR_QCA9533:
  406. ++ ath79_soc = ATH79_SOC_QCA9533;
  407. ++ chip = "9533";
  408. ++ rev = id & AR944X_REV_ID_REVISION_MASK;
  409. ++ break;
  410. ++
  411. + case REV_ID_MAJOR_QCA9558:
  412. + ath79_soc = ATH79_SOC_QCA9558;
  413. + chip = "9558";
  414. +@@ -176,7 +182,7 @@ static void __init ath79_detect_sys_type
  415. +
  416. + ath79_soc_rev = rev;
  417. +
  418. +- if (soc_is_qca955x())
  419. ++ if (soc_is_qca953x() || soc_is_qca955x())
  420. + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
  421. + chip, rev);
  422. + else
  423. +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  424. ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
  425. +@@ -106,6 +106,9 @@
  426. + #define AR934X_NFC_BASE 0x1b000200
  427. + #define AR934X_NFC_SIZE 0xb8
  428. +
  429. ++#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
  430. ++#define QCA953X_WMAC_SIZE 0x20000
  431. ++
  432. + #define QCA955X_PCI_MEM_BASE0 0x10000000
  433. + #define QCA955X_PCI_MEM_BASE1 0x12000000
  434. + #define QCA955X_PCI_MEM_SIZE 0x02000000
  435. +@@ -280,6 +283,43 @@
  436. +
  437. + #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
  438. +
  439. ++#define QCA953X_PLL_CPU_CONFIG_REG 0x00
  440. ++#define QCA953X_PLL_DDR_CONFIG_REG 0x04
  441. ++#define QCA953X_PLL_CLK_CTRL_REG 0x08
  442. ++#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
  443. ++#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
  444. ++
  445. ++#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
  446. ++#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
  447. ++#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
  448. ++#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
  449. ++#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
  450. ++#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
  451. ++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
  452. ++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
  453. ++
  454. ++#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
  455. ++#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
  456. ++#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
  457. ++#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
  458. ++#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
  459. ++#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
  460. ++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
  461. ++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
  462. ++
  463. ++#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
  464. ++#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
  465. ++#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
  466. ++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
  467. ++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
  468. ++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
  469. ++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
  470. ++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
  471. ++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
  472. ++#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
  473. ++#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
  474. ++#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  475. ++
  476. + #define QCA955X_PLL_CPU_CONFIG_REG 0x00
  477. + #define QCA955X_PLL_DDR_CONFIG_REG 0x04
  478. + #define QCA955X_PLL_CLK_CTRL_REG 0x08
  479. +@@ -354,6 +394,10 @@
  480. + #define AR934X_RESET_REG_BOOTSTRAP 0xb0
  481. + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
  482. +
  483. ++#define QCA953X_RESET_REG_RESET_MODULE 0x1c
  484. ++#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
  485. ++#define QCA953X_RESET_REG_EXT_INT_STATUS 0xac
  486. ++
  487. + #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
  488. + #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
  489. +
  490. +@@ -468,6 +512,8 @@
  491. + #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
  492. + #define AR934X_BOOTSTRAP_DDR1 BIT(0)
  493. +
  494. ++#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
  495. ++
  496. + #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
  497. +
  498. + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
  499. +@@ -530,6 +576,7 @@
  500. + #define REV_ID_MAJOR_AR9341 0x0120
  501. + #define REV_ID_MAJOR_AR9342 0x1120
  502. + #define REV_ID_MAJOR_AR9344 0x2120
  503. ++#define REV_ID_MAJOR_QCA9533 0x0140
  504. + #define REV_ID_MAJOR_QCA9558 0x1130
  505. +
  506. + #define AR71XX_REV_ID_MINOR_MASK 0x3
  507. +@@ -603,6 +650,7 @@
  508. + #define AR913X_GPIO_COUNT 22
  509. + #define AR933X_GPIO_COUNT 30
  510. + #define AR934X_GPIO_COUNT 23
  511. ++#define QCA953X_GPIO_COUNT 24 /* (?) */
  512. + #define QCA955X_GPIO_COUNT 24
  513. +
  514. + /*
  515. +--- a/arch/mips/include/asm/mach-ath79/ath79.h
  516. ++++ b/arch/mips/include/asm/mach-ath79/ath79.h
  517. +@@ -32,6 +32,7 @@ enum ath79_soc_type {
  518. + ATH79_SOC_AR9341,
  519. + ATH79_SOC_AR9342,
  520. + ATH79_SOC_AR9344,
  521. ++ ATH79_SOC_QCA9533,
  522. + ATH79_SOC_QCA9558,
  523. + };
  524. +
  525. +@@ -99,6 +100,16 @@ static inline int soc_is_ar934x(void)
  526. + return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
  527. + }
  528. +
  529. ++static inline int soc_is_qca9533(void)
  530. ++{
  531. ++ return ath79_soc == ATH79_SOC_QCA9533;
  532. ++}
  533. ++
  534. ++static inline int soc_is_qca953x(void)
  535. ++{
  536. ++ return soc_is_qca9533();
  537. ++}
  538. ++
  539. + static inline int soc_is_qca9558(void)
  540. + {
  541. + return ath79_soc == ATH79_SOC_QCA9558;