0036-ath79-dev-eth-fix-QCA9561-set-phy-interface-mode-and-mask.patch 1.5 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546
  1. From: Matthias Schiffer <mschiffer@universe-factory.net>
  2. Date: Fri, 13 May 2016 20:59:44 +0200
  3. Subject: ath79: dev-eth: fix QCA9561 set phy interface mode and mask
  4. QCA9563 and QCA9561 are two series of Qualcomm SoC Dragonfly. The only different
  5. is QCA9563 w/o internal switch. It has one GMAC with SGMII interface. But they
  6. have the same device ID(0x1150). So they share the same codes.
  7. Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
  8. Backport of OpenWrt r46971
  9. diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  10. index ff94e2e..31d2438 100644
  11. --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  12. +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
  13. @@ -633,7 +633,6 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
  14. case ATH79_SOC_AR9330:
  15. case ATH79_SOC_AR9331:
  16. case ATH79_SOC_QCA9533:
  17. - case ATH79_SOC_QCA9561:
  18. case ATH79_SOC_TP9343:
  19. pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
  20. break;
  21. @@ -667,6 +666,11 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
  22. }
  23. break;
  24. + case ATH79_SOC_QCA9561:
  25. + if (!pdata->phy_if_mode)
  26. + pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
  27. + break;
  28. +
  29. default:
  30. BUG();
  31. }
  32. @@ -1035,7 +1039,8 @@ void __init ath79_register_eth(unsigned int id)
  33. AR933X_RESET_GE0_MDIO;
  34. pdata->set_speed = ath79_set_speed_dummy;
  35. - pdata->phy_mask = BIT(4);
  36. + if (!pdata->phy_mask)
  37. + pdata->phy_mask = BIT(4);
  38. } else {
  39. pdata->reset_bit = AR933X_RESET_GE1_MAC |
  40. AR933X_RESET_GE1_MDIO;