From: Matthias Schiffer Date: Sat, 29 Mar 2014 21:55:41 +0100 Subject: ar71xx: add support for QCA953x SoC diff --git a/target/linux/ar71xx/config-3.3 b/target/linux/ar71xx/config-3.3 index dfc5bf2..1c3ba3c 100644 --- a/target/linux/ar71xx/config-3.3 +++ b/target/linux/ar71xx/config-3.3 @@ -40,11 +40,11 @@ CONFIG_ATH79_MACH_EW_DORIN=y CONFIG_ATH79_MACH_HORNET_UB=y CONFIG_ATH79_MACH_JA76PF=y CONFIG_ATH79_MACH_JWAP003=y +CONFIG_ATH79_MACH_MR600=y CONFIG_ATH79_MACH_MZK_W04NU=y CONFIG_ATH79_MACH_MZK_W300NH=y CONFIG_ATH79_MACH_NBG460N=y CONFIG_ATH79_MACH_OM2P=y -CONFIG_ATH79_MACH_MR600=y CONFIG_ATH79_MACH_PB42=y CONFIG_ATH79_MACH_PB44=y CONFIG_ATH79_MACH_PB92=y @@ -214,6 +214,7 @@ CONFIG_SOC_AR724X=y CONFIG_SOC_AR913X=y CONFIG_SOC_AR933X=y CONFIG_SOC_AR934X=y +CONFIG_SOC_QCA953X=y CONFIG_SOC_QCA955X=y CONFIG_SPI=y CONFIG_SPI_AP83=y diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index 5a0b950..1a9b0df 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -195,6 +195,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: mdio_dev = &ath79_mdio1_device; mdio_data = &ath79_mdio1_data; break; @@ -250,6 +251,11 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask) } mdio_data->is_ar934x = 1; break; + + case ATH79_SOC_QCA9533: + mdio_data->builtin_switch = 1; + break; + case ATH79_SOC_QCA9558: if (id == 1) mdio_data->builtin_switch = 1; @@ -540,6 +546,7 @@ static void __init ath79_init_eth_pll_data(unsigned int id) case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: + case ATH79_SOC_QCA9533: case ATH79_SOC_QCA9558: pll_10 = AR934X_PLL_VAL_10; pll_100 = AR934X_PLL_VAL_100; @@ -596,6 +603,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: pdata->phy_if_mode = PHY_INTERFACE_MODE_MII; break; @@ -645,6 +653,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id, case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII; break; @@ -882,6 +891,37 @@ void __init ath79_register_eth(unsigned int id) pdata->fifo_cfg3 = 0x01f00140; break; + case ATH79_SOC_QCA9533: + if (id == 0) { + pdata->reset_bit = AR933X_RESET_GE0_MAC | + AR933X_RESET_GE0_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->phy_mask = BIT(4); + } else { + pdata->reset_bit = AR933X_RESET_GE1_MAC | + AR933X_RESET_GE1_MDIO; + pdata->set_speed = ath79_set_speed_dummy; + + pdata->speed = SPEED_1000; + pdata->duplex = DUPLEX_FULL; + pdata->switch_data = &ath79_switch_data; + + ath79_switch_data.phy_poll_mask |= BIT(4); + } + + pdata->ddr_flush = ath79_ddr_no_flush; + pdata->has_gbit = 1; + pdata->is_ar724x = 1; + + if (!pdata->fifo_cfg1) + pdata->fifo_cfg1 = 0x0010ffff; + if (!pdata->fifo_cfg2) + pdata->fifo_cfg2 = 0x015500aa; + if (!pdata->fifo_cfg3) + pdata->fifo_cfg3 = 0x01f00140; + break; + case ATH79_SOC_AR9341: case ATH79_SOC_AR9342: case ATH79_SOC_AR9344: @@ -953,6 +993,7 @@ void __init ath79_register_eth(unsigned int id) case ATH79_SOC_AR7241: case ATH79_SOC_AR9330: case ATH79_SOC_AR9331: + case ATH79_SOC_QCA9533: pdata->mii_bus_dev = &ath79_mdio1_device.dev; break; diff --git a/target/linux/ar71xx/patches-3.3/705-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.3/705-MIPS-ath79-add-support-for-QCA953x-SoC.patch new file mode 100644 index 0000000..bd08685 --- /dev/null +++ b/target/linux/ar71xx/patches-3.3/705-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -0,0 +1,584 @@ +From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001 +Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net> +From: Matthias Schiffer +Date: Sat, 29 Mar 2014 20:26:08 +0100 +Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC + +Note that the clock calculation looks very similar to the QCA955x, but actually +some bits' meanings are slightly different. +--- + arch/mips/ath79/Kconfig | 6 +- + arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++ + arch/mips/ath79/common.c | 4 ++ + arch/mips/ath79/dev-common.c | 1 + + arch/mips/ath79/dev-wmac.c | 20 +++++++ + arch/mips/ath79/early_printk.c | 1 + + arch/mips/ath79/gpio.c | 4 +- + arch/mips/ath79/irq.c | 4 ++ + arch/mips/ath79/setup.c | 8 ++- + arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++ + arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++ + 11 files changed, 182 insertions(+), 3 deletions(-) + +--- a/arch/mips/ath79/Kconfig ++++ b/arch/mips/ath79/Kconfig +@@ -698,6 +698,10 @@ config SOC_AR934X + select PCI_AR724X if PCI + def_bool n + ++config SOC_QCA953X ++ select USB_ARCH_HAS_EHCI ++ def_bool n ++ + config SOC_QCA955X + select USB_ARCH_HAS_EHCI + select HW_HAS_PCI +@@ -741,7 +745,7 @@ config ATH79_DEV_USB + def_bool n + + config ATH79_DEV_WMAC +- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) ++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X) + def_bool n + + config ATH79_NVRAM +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo + iounmap(dpll_base); + } + ++static void __init qca953x_clocks_init(void) ++{ ++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ++ u32 cpu_pll, ddr_pll; ++ u32 bootstrap; ++ ++ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); ++ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40) ++ ath79_ref_clk.rate = 40 * 1000 * 1000; ++ else ++ ath79_ref_clk.rate = 25 * 1000 * 1000; ++ ++ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG); ++ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK; ++ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_NINT_MASK; ++ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & ++ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK; ++ ++ cpu_pll = nint * ath79_ref_clk.rate / ref_div; ++ cpu_pll += frac * (ath79_ref_clk.rate >> 6) / ref_div; ++ cpu_pll /= (1 << out_div); ++ ++ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG); ++ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK; ++ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK; ++ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_NINT_MASK; ++ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) & ++ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK; ++ ++ ddr_pll = nint * ath79_ref_clk.rate / ref_div; ++ ddr_pll += frac * (ath79_ref_clk.rate >> 6) / (ref_div << 4); ++ ddr_pll /= (1 << out_div); ++ ++ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG); ++ ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & ++ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS) ++ ath79_cpu_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) ++ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1); ++ else ++ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & ++ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS) ++ ath79_ddr_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) ++ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1); ++ else ++ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1); ++ ++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & ++ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; ++ ++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS) ++ ath79_ahb_clk.rate = ath79_ref_clk.rate; ++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) ++ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1); ++ else ++ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1); ++ ++ ath79_wdt_clk.rate = ath79_ref_clk.rate; ++ ath79_uart_clk.rate = ath79_ref_clk.rate; ++} ++ + static void __init qca955x_clocks_init(void) + { + u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; +@@ -383,6 +459,8 @@ void __init ath79_clocks_init(void) + ar933x_clocks_init(); + else if (soc_is_ar934x()) + ar934x_clocks_init(); ++ else if (soc_is_qca953x()) ++ qca953x_clocks_init(); + else if (soc_is_qca955x()) + qca955x_clocks_init(); + else +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -71,9 +71,12 @@ void ath79_device_reset_set(u32 mask) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; +- else if (soc_is_ar934x() || +- soc_is_qca955x()) ++ else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca953x()) ++ reg = QCA953X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca955x()) ++ reg = QCA955X_RESET_REG_RESET_MODULE; + else + BUG(); + +@@ -98,9 +101,12 @@ void ath79_device_reset_clear(u32 mask) + reg = AR913X_RESET_REG_RESET_MODULE; + else if (soc_is_ar933x()) + reg = AR933X_RESET_REG_RESET_MODULE; +- else if (soc_is_ar934x() || +- soc_is_qca955x()) ++ else if (soc_is_ar934x()) + reg = AR934X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca953x()) ++ reg = QCA953X_RESET_REG_RESET_MODULE; ++ else if (soc_is_qca955x()) ++ reg = QCA955X_RESET_REG_RESET_MODULE; + else + BUG(); + +--- a/arch/mips/ath79/dev-common.c ++++ b/arch/mips/ath79/dev-common.c +@@ -100,6 +100,7 @@ void __init ath79_register_uart(void) + soc_is_ar724x() || + soc_is_ar913x() || + soc_is_ar934x() || ++ soc_is_qca953x() || + soc_is_qca955x()) { + ath79_uart_data[0].uartclk = clk_get_rate(clk); + platform_device_register(&ath79_uart_device); +--- a/arch/mips/ath79/dev-wmac.c ++++ b/arch/mips/ath79/dev-wmac.c +@@ -147,6 +147,24 @@ static void ar934x_wmac_setup(void) + ath79_wmac_data.is_clk_25mhz = true; + } + ++static void qca953x_wmac_setup(void) ++{ ++ u32 t; ++ ++ ath79_wmac_device.name = "qca953x_wmac"; ++ ++ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE; ++ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1; ++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2; ++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2; ++ ++ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP); ++ if (t & QCA953X_BOOTSTRAP_REF_CLK_40) ++ ath79_wmac_data.is_clk_25mhz = false; ++ else ++ ath79_wmac_data.is_clk_25mhz = true; ++} ++ + static void qca955x_wmac_setup(void) + { + u32 t; +@@ -314,6 +332,8 @@ void __init ath79_register_wmac(u8 *cal_ + ar933x_wmac_setup(); + else if (soc_is_ar934x()) + ar934x_wmac_setup(); ++ else if (soc_is_qca953x()) ++ qca953x_wmac_setup(); + else if (soc_is_qca955x()) + qca955x_wmac_setup(); + else +--- a/arch/mips/ath79/early_printk.c ++++ b/arch/mips/ath79/early_printk.c +@@ -114,6 +114,7 @@ static void prom_putchar_init(void) + case REV_ID_MAJOR_AR9341: + case REV_ID_MAJOR_AR9342: + case REV_ID_MAJOR_AR9344: ++ case REV_ID_MAJOR_QCA9533: + case REV_ID_MAJOR_QCA9558: + _prom_putchar = prom_putchar_ar71xx; + break; +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -232,14 +232,18 @@ void __init ath79_gpio_init(void) + + if (soc_is_ar71xx()) + ath79_gpio_count = AR71XX_GPIO_COUNT; +- else if (soc_is_ar724x()) +- ath79_gpio_count = AR724X_GPIO_COUNT; ++ else if (soc_is_ar7240()) ++ ath79_gpio_count = AR7240_GPIO_COUNT; ++ else if (soc_is_ar7241() || soc_is_ar7242()) ++ ath79_gpio_count = AR7241_GPIO_COUNT; + else if (soc_is_ar913x()) + ath79_gpio_count = AR913X_GPIO_COUNT; + else if (soc_is_ar933x()) + ath79_gpio_count = AR933X_GPIO_COUNT; + else if (soc_is_ar934x()) + ath79_gpio_count = AR934X_GPIO_COUNT; ++ else if (soc_is_qca953x()) ++ ath79_gpio_count = QCA953X_GPIO_COUNT; + else if (soc_is_qca955x()) + ath79_gpio_count = QCA955X_GPIO_COUNT; + else +@@ -247,7 +251,7 @@ void __init ath79_gpio_init(void) + + ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + ath79_gpio_chip.ngpio = ath79_gpio_count; +- if (soc_is_ar934x() || soc_is_qca955x()) { ++ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) { + ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; + ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; + } +--- a/arch/mips/ath79/irq.c ++++ b/arch/mips/ath79/irq.c +@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v + else if (soc_is_ar724x() || + soc_is_ar933x() || + soc_is_ar934x() || ++ soc_is_qca953x() || + soc_is_qca955x()) + ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; + else +@@ -352,6 +353,9 @@ void __init arch_init_irq(void) + } else if (soc_is_ar934x()) { + ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ar934x_ip3_handler; ++ } else if (soc_is_qca953x()) { ++ ath79_ip2_handler = ath79_default_ip2_handler; ++ ath79_ip3_handler = ath79_default_ip3_handler; + } else if (soc_is_qca955x()) { + ath79_ip2_handler = ath79_default_ip2_handler; + ath79_ip3_handler = ath79_default_ip3_handler; +--- a/arch/mips/ath79/setup.c ++++ b/arch/mips/ath79/setup.c +@@ -164,10 +164,16 @@ static void __init ath79_detect_sys_type + rev = id & AR934X_REV_ID_REVISION_MASK; + break; + ++ case REV_ID_MAJOR_QCA9533: ++ ath79_soc = ATH79_SOC_QCA9533; ++ chip = "9533"; ++ rev = id & QCA955X_REV_ID_REVISION_MASK; ++ break; ++ + case REV_ID_MAJOR_QCA9558: + ath79_soc = ATH79_SOC_QCA9558; + chip = "9558"; +- rev = id & AR944X_REV_ID_REVISION_MASK; ++ rev = id & QCA955X_REV_ID_REVISION_MASK; + break; + + default: +@@ -176,7 +182,7 @@ static void __init ath79_detect_sys_type + + ath79_soc_rev = rev; + +- if (soc_is_qca955x()) ++ if (soc_is_qca953x() || soc_is_qca955x()) + sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u", + chip, rev); + else +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -38,8 +38,8 @@ + #define AR71XX_UART_SIZE 0x100 + #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) + #define AR71XX_USB_CTRL_SIZE 0x100 +-#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +-#define AR71XX_GPIO_SIZE 0x100 ++#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) ++#define AR71XX_GPIO_SIZE 0x100 + #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) + #define AR71XX_PLL_SIZE 0x100 + #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) +@@ -101,10 +101,13 @@ + #define AR934X_WMAC_SIZE 0x20000 + #define AR934X_EHCI_BASE 0x1b000000 + #define AR934X_EHCI_SIZE 0x200 +-#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) +-#define AR934X_SRIF_SIZE 0x1000 + #define AR934X_NFC_BASE 0x1b000200 + #define AR934X_NFC_SIZE 0xb8 ++#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) ++#define AR934X_SRIF_SIZE 0x1000 ++ ++#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) ++#define QCA953X_WMAC_SIZE 0x20000 + + #define QCA955X_PCI_MEM_BASE0 0x10000000 + #define QCA955X_PCI_MEM_BASE1 0x12000000 +@@ -119,14 +122,14 @@ + #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) + #define QCA955X_PCI_CTRL_SIZE 0x100 + ++#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) ++#define QCA955X_GMAC_SIZE 0x40 + #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) + #define QCA955X_WMAC_SIZE 0x20000 + #define QCA955X_EHCI0_BASE 0x1b000000 + #define QCA955X_EHCI1_BASE 0x1b400000 +-#define QCA955X_EHCI_SIZE 0x200 +-#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) +-#define QCA955X_GMAC_SIZE 0x40 +-#define QCA955X_NFC_BASE 0x1b000200 ++#define QCA955X_EHCI_SIZE 0x1000 ++#define QCA955X_NFC_BASE 0x1b800200 + #define QCA955X_NFC_SIZE 0xb8 + + #define AR9300_OTP_BASE 0x14000 +@@ -280,9 +283,48 @@ + + #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) + ++#define QCA953X_PLL_CPU_CONFIG_REG 0x00 ++#define QCA953X_PLL_DDR_CONFIG_REG 0x04 ++#define QCA953X_PLL_CLK_CTRL_REG 0x08 ++#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c ++#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48 ++ ++#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 ++#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f ++#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 ++#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f ++#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 ++#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f ++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 ++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 ++ ++#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 ++#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff ++#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 ++#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f ++#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 ++#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f ++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 ++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 ++ ++#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) ++#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) ++#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) ++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 ++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f ++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 ++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f ++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 ++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f ++#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) ++#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) ++#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) ++ + #define QCA955X_PLL_CPU_CONFIG_REG 0x00 + #define QCA955X_PLL_DDR_CONFIG_REG 0x04 + #define QCA955X_PLL_CLK_CTRL_REG 0x08 ++#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 ++#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + + #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 + #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +@@ -354,6 +396,11 @@ + #define AR934X_RESET_REG_BOOTSTRAP 0xb0 + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + ++#define QCA953X_RESET_REG_RESET_MODULE 0x1c ++#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 ++#define QCA953X_RESET_REG_EXT_INT_STATUS 0xac ++ ++#define QCA955X_RESET_REG_RESET_MODULE 0x1c + #define QCA955X_RESET_REG_BOOTSTRAP 0xb0 + #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +@@ -448,6 +495,39 @@ + #define AR934X_RESET_MBOX BIT(1) + #define AR934X_RESET_I2S BIT(0) + ++#define QCA955X_RESET_HOST BIT(31) ++#define QCA955X_RESET_SLIC BIT(30) ++#define QCA955X_RESET_HDMA BIT(29) ++#define QCA955X_RESET_EXTERNAL BIT(28) ++#define QCA955X_RESET_RTC BIT(27) ++#define QCA955X_RESET_PCIE_EP_INT BIT(26) ++#define QCA955X_RESET_CHKSUM_ACC BIT(25) ++#define QCA955X_RESET_FULL_CHIP BIT(24) ++#define QCA955X_RESET_GE1_MDIO BIT(23) ++#define QCA955X_RESET_GE0_MDIO BIT(22) ++#define QCA955X_RESET_CPU_NMI BIT(21) ++#define QCA955X_RESET_CPU_COLD BIT(20) ++#define QCA955X_RESET_HOST_RESET_INT BIT(19) ++#define QCA955X_RESET_PCIE_EP BIT(18) ++#define QCA955X_RESET_UART1 BIT(17) ++#define QCA955X_RESET_DDR BIT(16) ++#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) ++#define QCA955X_RESET_NANDF BIT(14) ++#define QCA955X_RESET_GE1_MAC BIT(13) ++#define QCA955X_RESET_SGMII_ANALOG BIT(12) ++#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) ++#define QCA955X_RESET_HOST_DMA_INT BIT(10) ++#define QCA955X_RESET_GE0_MAC BIT(9) ++#define QCA955X_RESET_SGMII BIT(8) ++#define QCA955X_RESET_PCIE_PHY BIT(7) ++#define QCA955X_RESET_PCIE BIT(6) ++#define QCA955X_RESET_USB_HOST BIT(5) ++#define QCA955X_RESET_USB_PHY BIT(4) ++#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) ++#define QCA955X_RESET_LUT BIT(2) ++#define QCA955X_RESET_MBOX BIT(1) ++#define QCA955X_RESET_I2S BIT(0) ++ + #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) + #define AR933X_BOOTSTRAP_EEPBUSY BIT(4) + #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) +@@ -465,9 +545,11 @@ + #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) + #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) + #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +-#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) ++#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) + #define AR934X_BOOTSTRAP_DDR1 BIT(0) + ++#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) ++ + #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + + #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +@@ -530,6 +612,8 @@ + #define REV_ID_MAJOR_AR9341 0x0120 + #define REV_ID_MAJOR_AR9342 0x1120 + #define REV_ID_MAJOR_AR9344 0x2120 ++#define REV_ID_MAJOR_QCA9533 0x0140 ++#define REV_ID_MAJOR_QCA9556 0x0130 + #define REV_ID_MAJOR_QCA9558 0x1130 + + #define AR71XX_REV_ID_MINOR_MASK 0x3 +@@ -549,9 +633,9 @@ + + #define AR724X_REV_ID_REVISION_MASK 0x3 + +-#define AR934X_REV_ID_REVISION_MASK 0xf ++#define AR934X_REV_ID_REVISION_MASK 0xf + +-#define AR944X_REV_ID_REVISION_MASK 0xf ++#define QCA955X_REV_ID_REVISION_MASK 0xf + + /* + * SPI block +@@ -599,10 +683,12 @@ + #define AR934X_GPIO_REG_FUNC 0x6c + + #define AR71XX_GPIO_COUNT 16 +-#define AR724X_GPIO_COUNT 18 ++#define AR7240_GPIO_COUNT 18 ++#define AR7241_GPIO_COUNT 20 + #define AR913X_GPIO_COUNT 22 + #define AR933X_GPIO_COUNT 30 + #define AR934X_GPIO_COUNT 23 ++#define QCA953X_GPIO_COUNT 24 /* (?) */ + #define QCA955X_GPIO_COUNT 24 + + /* +@@ -693,12 +779,14 @@ + #define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) + #define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) + +-#define AR934X_GPIO_OUT_GPIO 0 +-#define AR934X_GPIO_OUT_LED_LINK0 41 +-#define AR934X_GPIO_OUT_LED_LINK1 42 +-#define AR934X_GPIO_OUT_LED_LINK2 43 +-#define AR934X_GPIO_OUT_LED_LINK3 44 +-#define AR934X_GPIO_OUT_LED_LINK4 45 ++#define AR934X_GPIO_OUT_GPIO 0 ++#define AR934X_GPIO_OUT_LED_LINK0 41 ++#define AR934X_GPIO_OUT_LED_LINK1 42 ++#define AR934X_GPIO_OUT_LED_LINK2 43 ++#define AR934X_GPIO_OUT_LED_LINK3 44 ++#define AR934X_GPIO_OUT_LED_LINK4 45 ++#define AR934X_GPIO_OUT_EXT_LNA0 46 ++#define AR934X_GPIO_OUT_EXT_LNA1 47 + + /* + * MII_CTRL block +@@ -756,6 +844,8 @@ + #define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) + #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) + #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) ++#define AR934X_ETH_CFG_RXD_DELAY BIT(14) ++#define AR934X_ETH_CFG_RDV_DELAY BIT(16) + + /* + * QCA955X GMAC Interface +@@ -763,7 +853,7 @@ + + #define QCA955X_GMAC_REG_ETH_CFG 0x00 + +-#define QCA955X_ETH_CFG_RGMII_GMAC0 BIT(0) +-#define QCA955X_ETH_CFG_SGMII_GMAC0 BIT(6) ++#define QCA955X_ETH_CFG_RGMII_EN BIT(0) ++#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) + + #endif /* __ASM_MACH_AR71XX_REGS_H */ +--- a/arch/mips/include/asm/mach-ath79/ath79.h ++++ b/arch/mips/include/asm/mach-ath79/ath79.h +@@ -32,6 +32,7 @@ enum ath79_soc_type { + ATH79_SOC_AR9341, + ATH79_SOC_AR9342, + ATH79_SOC_AR9344, ++ ATH79_SOC_QCA9533, + ATH79_SOC_QCA9558, + }; + +@@ -99,6 +100,16 @@ static inline int soc_is_ar934x(void) + return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); + } + ++static inline int soc_is_qca9533(void) ++{ ++ return ath79_soc == ATH79_SOC_QCA9533; ++} ++ ++static inline int soc_is_qca953x(void) ++{ ++ return soc_is_qca9533(); ++} ++ + static inline int soc_is_qca9558(void) + { + return ath79_soc == ATH79_SOC_QCA9558; +--- a/arch/mips/ath79/mach-ap136.c ++++ b/arch/mips/ath79/mach-ap136.c +@@ -149,8 +149,8 @@ static void __init ap136_gmac_setup(void + + t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG); + +- t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0); +- t |= QCA955X_ETH_CFG_RGMII_GMAC0; ++ t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII); ++ t |= QCA955X_ETH_CFG_RGMII_EN; + + __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG); +