Clean up QCA953x support patch

patches/openwrt/0018-ar71xx-add-support-for-QCA953x-SoC.patch

@@ -123,10 +123,10 @@ index 5a0b950..1a9b0df 100644
  
 diff --git a/target/linux/ar71xx/patches-3.3/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.3/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
 new file mode 100644
-index 0000000..063af94
+index 0000000..4c9e761
 --- /dev/null
 +++ b/target/linux/ar71xx/patches-3.3/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
-@@ -0,0 +1,604 @@
+@@ -0,0 +1,417 @@
 +From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
 +Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
 +From: Matthias Schiffer <mschiffer@universe-factory.net>
@@ -267,33 +267,21 @@ index 0000000..063af94
 + 	else
 +--- a/arch/mips/ath79/common.c
 ++++ b/arch/mips/ath79/common.c
-+@@ -71,9 +71,12 @@ void ath79_device_reset_set(u32 mask)
-+ 		reg = AR913X_RESET_REG_RESET_MODULE;
-+ 	else if (soc_is_ar933x())
-+ 		reg = AR933X_RESET_REG_RESET_MODULE;
-+-	else if (soc_is_ar934x() ||
-+-		 soc_is_qca955x())
-++	else if (soc_is_ar934x())
++@@ -74,6 +74,8 @@ void ath79_device_reset_set(u32 mask)
++ 	else if (soc_is_ar934x() ||
++ 		 soc_is_qca955x())
 + 		reg = AR934X_RESET_REG_RESET_MODULE;
 ++	else if (soc_is_qca953x())
 ++		reg = QCA953X_RESET_REG_RESET_MODULE;
-++	else if (soc_is_qca955x())
-++		reg = QCA955X_RESET_REG_RESET_MODULE;
 + 	else
 + 		BUG();
 + 
-+@@ -98,9 +101,12 @@ void ath79_device_reset_clear(u32 mask)
-+ 		reg = AR913X_RESET_REG_RESET_MODULE;
-+ 	else if (soc_is_ar933x())
-+ 		reg = AR933X_RESET_REG_RESET_MODULE;
-+-	else if (soc_is_ar934x() ||
-+-		 soc_is_qca955x())
-++	else if (soc_is_ar934x())
++@@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
++ 	else if (soc_is_ar934x() ||
++ 		 soc_is_qca955x())
 + 		reg = AR934X_RESET_REG_RESET_MODULE;
 ++	else if (soc_is_qca953x())
 ++		reg = QCA953X_RESET_REG_RESET_MODULE;
-++	else if (soc_is_qca955x())
-++		reg = QCA955X_RESET_REG_RESET_MODULE;
 + 	else
 + 		BUG();
 + 
@@ -375,19 +363,7 @@ index 0000000..063af94
 + 		break;
 +--- a/arch/mips/ath79/gpio.c
 ++++ b/arch/mips/ath79/gpio.c
-+@@ -232,14 +232,18 @@ void __init ath79_gpio_init(void)
-+ 
-+ 	if (soc_is_ar71xx())
-+ 		ath79_gpio_count = AR71XX_GPIO_COUNT;
-+-	else if (soc_is_ar724x())
-+-		ath79_gpio_count = AR724X_GPIO_COUNT;
-++	else if (soc_is_ar7240())
-++		ath79_gpio_count = AR7240_GPIO_COUNT;
-++	else if (soc_is_ar7241() || soc_is_ar7242())
-++		ath79_gpio_count = AR7241_GPIO_COUNT;
-+ 	else if (soc_is_ar913x())
-+ 		ath79_gpio_count = AR913X_GPIO_COUNT;
-+ 	else if (soc_is_ar933x())
++@@ -240,6 +240,8 @@ void __init ath79_gpio_init(void)
 + 		ath79_gpio_count = AR933X_GPIO_COUNT;
 + 	else if (soc_is_ar934x())
 + 		ath79_gpio_count = AR934X_GPIO_COUNT;
@@ -396,7 +372,7 @@ index 0000000..063af94
 + 	else if (soc_is_qca955x())
 + 		ath79_gpio_count = QCA955X_GPIO_COUNT;
 + 	else
-+@@ -247,7 +251,7 @@ void __init ath79_gpio_init(void)
++@@ -247,7 +249,7 @@ void __init ath79_gpio_init(void)
 + 
 + 	ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 + 	ath79_gpio_chip.ngpio = ath79_gpio_count;
@@ -427,24 +403,19 @@ index 0000000..063af94
 + 		ath79_ip3_handler = ath79_default_ip3_handler;
 +--- a/arch/mips/ath79/setup.c
 ++++ b/arch/mips/ath79/setup.c
-+@@ -164,10 +164,16 @@ static void __init ath79_detect_sys_type
++@@ -164,6 +164,12 @@ static void __init ath79_detect_sys_type
 + 		rev = id & AR934X_REV_ID_REVISION_MASK;
 + 		break;
 + 
 ++	case REV_ID_MAJOR_QCA9533:
 ++		ath79_soc = ATH79_SOC_QCA9533;
 ++		chip = "9533";
-++		rev = id & QCA955X_REV_ID_REVISION_MASK;
+++		rev = id & AR944X_REV_ID_REVISION_MASK;
 ++		break;
 ++
 + 	case REV_ID_MAJOR_QCA9558:
 + 		ath79_soc = ATH79_SOC_QCA9558;
 + 		chip = "9558";
-+-		rev = id & AR944X_REV_ID_REVISION_MASK;
-++		rev = id & QCA955X_REV_ID_REVISION_MASK;
-+ 		break;
-+ 
-+ 	default:
 +@@ -176,7 +182,7 @@ static void __init ath79_detect_sys_type
 + 
 + 	ath79_soc_rev = rev;
@@ -456,53 +427,17 @@ index 0000000..063af94
 + 	else
 +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
-+@@ -38,8 +38,8 @@
-+ #define AR71XX_UART_SIZE	0x100
-+ #define AR71XX_USB_CTRL_BASE	(AR71XX_APB_BASE + 0x00030000)
-+ #define AR71XX_USB_CTRL_SIZE	0x100
-+-#define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
-+-#define AR71XX_GPIO_SIZE        0x100
-++#define AR71XX_GPIO_BASE	(AR71XX_APB_BASE + 0x00040000)
-++#define AR71XX_GPIO_SIZE	0x100
-+ #define AR71XX_PLL_BASE		(AR71XX_APB_BASE + 0x00050000)
-+ #define AR71XX_PLL_SIZE		0x100
-+ #define AR71XX_RESET_BASE	(AR71XX_APB_BASE + 0x00060000)
-+@@ -101,10 +101,13 @@
-+ #define AR934X_WMAC_SIZE	0x20000
-+ #define AR934X_EHCI_BASE	0x1b000000
-+ #define AR934X_EHCI_SIZE	0x200
-+-#define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
-+-#define AR934X_SRIF_SIZE	0x1000
++@@ -106,6 +106,9 @@
 + #define AR934X_NFC_BASE		0x1b000200
 + #define AR934X_NFC_SIZE		0xb8
-++#define AR934X_SRIF_BASE	(AR71XX_APB_BASE + 0x00116000)
-++#define AR934X_SRIF_SIZE	0x1000
-++
++ 
 ++#define QCA953X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
 ++#define QCA953X_WMAC_SIZE	0x20000
-+ 
+++
 + #define QCA955X_PCI_MEM_BASE0	0x10000000
 + #define QCA955X_PCI_MEM_BASE1	0x12000000
-+@@ -119,14 +122,14 @@
-+ #define QCA955X_PCI_CTRL_BASE1	(AR71XX_APB_BASE + 0x00280000)
-+ #define QCA955X_PCI_CTRL_SIZE	0x100
-+ 
-++#define QCA955X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
-++#define QCA955X_GMAC_SIZE	0x40
-+ #define QCA955X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
-+ #define QCA955X_WMAC_SIZE	0x20000
-+ #define QCA955X_EHCI0_BASE	0x1b000000
-+ #define QCA955X_EHCI1_BASE	0x1b400000
-+-#define QCA955X_EHCI_SIZE	0x200
-+-#define QCA955X_GMAC_BASE	(AR71XX_APB_BASE + 0x00070000)
-+-#define QCA955X_GMAC_SIZE	0x40
-+-#define QCA955X_NFC_BASE	0x1b000200
-++#define QCA955X_EHCI_SIZE	0x1000
-++#define QCA955X_NFC_BASE	0x1b800200
-+ #define QCA955X_NFC_SIZE	0xb8
-+ 
-+ #define AR9300_OTP_BASE		0x14000
-+@@ -280,9 +283,48 @@
++ #define QCA955X_PCI_MEM_SIZE	0x02000000
++@@ -280,6 +283,43 @@
 + 
 + #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL	BIT(6)
 + 
@@ -546,12 +481,7 @@ index 0000000..063af94
 + #define QCA955X_PLL_CPU_CONFIG_REG		0x00
 + #define QCA955X_PLL_DDR_CONFIG_REG		0x04
 + #define QCA955X_PLL_CLK_CTRL_REG		0x08
-++#define QCA955X_PLL_ETH_XMII_CONTROL_REG	0x28
-++#define QCA955X_PLL_ETH_SGMII_CONTROL_REG	0x48
-+ 
-+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
-+ #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
-+@@ -354,6 +396,11 @@
++@@ -354,6 +394,10 @@
 + #define AR934X_RESET_REG_BOOTSTRAP		0xb0
 + #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
 + 
@@ -559,56 +489,11 @@ index 0000000..063af94
 ++#define QCA953X_RESET_REG_BOOTSTRAP		0xb0
 ++#define QCA953X_RESET_REG_EXT_INT_STATUS	0xac
 ++
-++#define QCA955X_RESET_REG_RESET_MODULE		0x1c
 + #define QCA955X_RESET_REG_BOOTSTRAP		0xb0
 + #define QCA955X_RESET_REG_EXT_INT_STATUS	0xac
 + 
-+@@ -448,6 +495,39 @@
-+ #define AR934X_RESET_MBOX		BIT(1)
-+ #define AR934X_RESET_I2S		BIT(0)
-+ 
-++#define QCA955X_RESET_HOST		BIT(31)
-++#define QCA955X_RESET_SLIC		BIT(30)
-++#define QCA955X_RESET_HDMA		BIT(29)
-++#define QCA955X_RESET_EXTERNAL		BIT(28)
-++#define QCA955X_RESET_RTC		BIT(27)
-++#define QCA955X_RESET_PCIE_EP_INT	BIT(26)
-++#define QCA955X_RESET_CHKSUM_ACC	BIT(25)
-++#define QCA955X_RESET_FULL_CHIP		BIT(24)
-++#define QCA955X_RESET_GE1_MDIO		BIT(23)
-++#define QCA955X_RESET_GE0_MDIO		BIT(22)
-++#define QCA955X_RESET_CPU_NMI		BIT(21)
-++#define QCA955X_RESET_CPU_COLD		BIT(20)
-++#define QCA955X_RESET_HOST_RESET_INT	BIT(19)
-++#define QCA955X_RESET_PCIE_EP		BIT(18)
-++#define QCA955X_RESET_UART1		BIT(17)
-++#define QCA955X_RESET_DDR		BIT(16)
-++#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
-++#define QCA955X_RESET_NANDF		BIT(14)
-++#define QCA955X_RESET_GE1_MAC		BIT(13)
-++#define QCA955X_RESET_SGMII_ANALOG	BIT(12)
-++#define QCA955X_RESET_USB_PHY_ANALOG	BIT(11)
-++#define QCA955X_RESET_HOST_DMA_INT	BIT(10)
-++#define QCA955X_RESET_GE0_MAC		BIT(9)
-++#define QCA955X_RESET_SGMII		BIT(8)
-++#define QCA955X_RESET_PCIE_PHY		BIT(7)
-++#define QCA955X_RESET_PCIE		BIT(6)
-++#define QCA955X_RESET_USB_HOST		BIT(5)
-++#define QCA955X_RESET_USB_PHY		BIT(4)
-++#define QCA955X_RESET_USBSUS_OVERRIDE	BIT(3)
-++#define QCA955X_RESET_LUT		BIT(2)
-++#define QCA955X_RESET_MBOX		BIT(1)
-++#define QCA955X_RESET_I2S		BIT(0)
-++
-+ #define AR933X_BOOTSTRAP_MDIO_GPIO_EN	BIT(18)
-+ #define AR933X_BOOTSTRAP_EEPBUSY	BIT(4)
-+ #define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
-+@@ -465,9 +545,11 @@
-+ #define AR934X_BOOTSTRAP_EJTAG_MODE	BIT(5)
-+ #define AR934X_BOOTSTRAP_REF_CLK_40	BIT(4)
-+ #define AR934X_BOOTSTRAP_BOOT_FROM_SPI	BIT(2)
-+-#define AR934X_BOOTSTRAP_SDRAM_DISABLED	BIT(1)
-++#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
++@@ -468,6 +512,8 @@
++ #define AR934X_BOOTSTRAP_SDRAM_DISABLED	BIT(1)
 + #define AR934X_BOOTSTRAP_DDR1		BIT(0)
 + 
 ++#define QCA953X_BOOTSTRAP_REF_CLK_40	BIT(4)
@@ -616,34 +501,15 @@ index 0000000..063af94
 + #define QCA955X_BOOTSTRAP_REF_CLK_40	BIT(4)
 + 
 + #define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
-+@@ -530,6 +612,8 @@
++@@ -530,6 +576,7 @@
 + #define REV_ID_MAJOR_AR9341		0x0120
 + #define REV_ID_MAJOR_AR9342		0x1120
 + #define REV_ID_MAJOR_AR9344		0x2120
 ++#define REV_ID_MAJOR_QCA9533		0x0140
-++#define REV_ID_MAJOR_QCA9556		0x0130
 + #define REV_ID_MAJOR_QCA9558		0x1130
 + 
 + #define AR71XX_REV_ID_MINOR_MASK	0x3
-+@@ -549,9 +633,9 @@
-+ 
-+ #define AR724X_REV_ID_REVISION_MASK	0x3
-+ 
-+-#define AR934X_REV_ID_REVISION_MASK     0xf
-++#define AR934X_REV_ID_REVISION_MASK	0xf
-+ 
-+-#define AR944X_REV_ID_REVISION_MASK	0xf
-++#define QCA955X_REV_ID_REVISION_MASK	0xf
-+ 
-+ /*
-+  * SPI block
-+@@ -599,10 +683,12 @@
-+ #define AR934X_GPIO_REG_FUNC		0x6c
-+ 
-+ #define AR71XX_GPIO_COUNT		16
-+-#define AR724X_GPIO_COUNT		18
-++#define AR7240_GPIO_COUNT		18
-++#define AR7241_GPIO_COUNT		20
++@@ -603,6 +650,7 @@
 + #define AR913X_GPIO_COUNT		22
 + #define AR933X_GPIO_COUNT		30
 + #define AR934X_GPIO_COUNT		23
@@ -651,46 +517,6 @@ index 0000000..063af94
 + #define QCA955X_GPIO_COUNT		24
 + 
 + /*
-+@@ -693,12 +779,14 @@
-+ #define AR934X_GPIO_FUNC_CLK_OBS0_EN		BIT(2)
-+ #define AR934X_GPIO_FUNC_JTAG_DISABLE		BIT(1)
-+ 
-+-#define AR934X_GPIO_OUT_GPIO          0
-+-#define AR934X_GPIO_OUT_LED_LINK0     41
-+-#define AR934X_GPIO_OUT_LED_LINK1     42
-+-#define AR934X_GPIO_OUT_LED_LINK2     43
-+-#define AR934X_GPIO_OUT_LED_LINK3     44
-+-#define AR934X_GPIO_OUT_LED_LINK4     45
-++#define AR934X_GPIO_OUT_GPIO		0
-++#define AR934X_GPIO_OUT_LED_LINK0	41
-++#define AR934X_GPIO_OUT_LED_LINK1	42
-++#define AR934X_GPIO_OUT_LED_LINK2	43
-++#define AR934X_GPIO_OUT_LED_LINK3	44
-++#define AR934X_GPIO_OUT_LED_LINK4	45
-++#define AR934X_GPIO_OUT_EXT_LNA0	46
-++#define AR934X_GPIO_OUT_EXT_LNA1	47
-+ 
-+ /*
-+  * MII_CTRL block
-+@@ -756,6 +844,8 @@
-+ #define AR933X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
-+ #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
-+ #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)
-++#define AR934X_ETH_CFG_RXD_DELAY        BIT(14)
-++#define AR934X_ETH_CFG_RDV_DELAY        BIT(16)
-+ 
-+ /*
-+  * QCA955X GMAC Interface
-+@@ -763,7 +853,7 @@
-+ 
-+ #define QCA955X_GMAC_REG_ETH_CFG	0x00
-+ 
-+-#define QCA955X_ETH_CFG_RGMII_GMAC0	BIT(0)
-+-#define QCA955X_ETH_CFG_SGMII_GMAC0	BIT(6)
-++#define QCA955X_ETH_CFG_RGMII_EN	BIT(0)
-++#define QCA955X_ETH_CFG_GE0_SGMII	BIT(6)
-+ 
-+ #endif /* __ASM_MACH_AR71XX_REGS_H */
 +--- a/arch/mips/include/asm/mach-ath79/ath79.h
 ++++ b/arch/mips/include/asm/mach-ath79/ath79.h
 +@@ -32,6 +32,7 @@ enum ath79_soc_type {
@@ -718,16 +544,3 @@ index 0000000..063af94
 + static inline int soc_is_qca9558(void)
 + {
 + 	return ath79_soc == ATH79_SOC_QCA9558;
-+--- a/arch/mips/ath79/mach-ap136.c
-++++ b/arch/mips/ath79/mach-ap136.c
-+@@ -149,8 +149,8 @@ static void __init ap136_gmac_setup(void
-+ 
-+ 	t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
-+ 
-+-	t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0);
-+-	t |= QCA955X_ETH_CFG_RGMII_GMAC0;
-++	t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
-++	t |= QCA955X_ETH_CFG_RGMII_EN;
-+ 
-+ 	__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
-+