|
@@ -103,25 +103,16 @@ index ae3db4c..ff94e2e 100644
|
|
|
break;
|
|
|
|
|
|
diff --git a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
|
|
|
-index 5041619..403897a 100644
|
|
|
+index f3b4446..cf10af3 100644
|
|
|
--- a/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
|
|
|
+++ b/target/linux/ar71xx/patches-3.18/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
|
|
|
-@@ -44,7 +44,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
- config ATH79_NVRAM
|
|
|
- --- a/arch/mips/ath79/clock.c
|
|
|
- +++ b/arch/mips/ath79/clock.c
|
|
|
--@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(vo
|
|
|
-+@@ -350,6 +350,91 @@ static void __init ar934x_clocks_init(void)
|
|
|
- iounmap(dpll_base);
|
|
|
- }
|
|
|
-
|
|
|
@@ -175,6 +175,48 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
soc_is_qca955x()) {
|
|
|
ath79_uart_data[0].uartclk = uart_clk_rate;
|
|
|
platform_device_register(&ath79_uart_device);
|
|
|
+--- a/arch/mips/ath79/dev-usb.c
|
|
|
++++ b/arch/mips/ath79/dev-usb.c
|
|
|
-+@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void)
|
|
|
++@@ -236,6 +236,30 @@ static void __init ar934x_usb_setup(void
|
|
|
+ &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
|
|
|
+ }
|
|
|
+
|
|
@@ -164,26 +155,6 @@ index 5041619..403897a 100644
|
|
|
--- a/arch/mips/ath79/dev-wmac.c
|
|
|
+++ b/arch/mips/ath79/dev-wmac.c
|
|
|
@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
|
|
|
-@@ -186,7 +228,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
- {
|
|
|
- return ath79_soc_rev;
|
|
|
- }
|
|
|
--@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
|
|
|
-+@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(void)
|
|
|
- ath79_wmac_data.is_clk_25mhz = true;
|
|
|
-
|
|
|
- if (ath79_soc_rev == 1)
|
|
|
-@@ -195,8 +237,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
-
|
|
|
- ath79_wmac_data.external_reset = ar933x_wmac_reset;
|
|
|
- }
|
|
|
--@@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
|
|
|
-- ath79_wmac_data.is_clk_25mhz = true;
|
|
|
-+@@ -151,6 +151,26 @@ static void ar934x_wmac_setup(void)
|
|
|
-+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
|
|
|
- }
|
|
|
-
|
|
|
- +static void qca953x_wmac_setup(void)
|
|
|
@@ -207,8 +249,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
+
|
|
|
+ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
|
|
@@ -195,20 +166,11 @@ index 5041619..403897a 100644
|
|
|
+
|
|
|
+ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
|
|
|
+ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
|
|
|
-@@ -222,7 +264,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
- static void qca955x_wmac_setup(void)
|
|
|
- {
|
|
|
- u32 t;
|
|
|
--@@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
|
|
|
-+@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
|
|
|
- ar933x_wmac_setup();
|
|
|
- else if (soc_is_ar934x())
|
|
|
- ar934x_wmac_setup();
|
|
|
@@ -244,6 +286,24 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
_prom_putchar = prom_putchar_ar71xx;
|
|
|
--- a/arch/mips/ath79/gpio.c
|
|
|
+++ b/arch/mips/ath79/gpio.c
|
|
|
-+@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_function_reg(void)
|
|
|
++@@ -148,7 +148,7 @@ static void __iomem *ath79_gpio_get_func
|
|
|
+ soc_is_ar913x() ||
|
|
|
+ soc_is_ar933x())
|
|
|
+ reg = AR71XX_GPIO_REG_FUNC;
|
|
@@ -217,7 +179,7 @@ index 5041619..403897a 100644
|
|
|
+ reg = AR934X_GPIO_REG_FUNC;
|
|
|
+ else
|
|
|
+ BUG();
|
|
|
-+@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(unsigned gpio, u8 val)
|
|
|
++@@ -187,7 +187,7 @@ void __init ath79_gpio_output_select(uns
|
|
|
+ unsigned int reg;
|
|
|
+ u32 t, s;
|
|
|
+
|
|
@@ -229,16 +191,7 @@ index 5041619..403897a 100644
|
|
|
@@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
|
|
|
ath79_gpio_count = AR933X_GPIO_COUNT;
|
|
|
else if (soc_is_ar934x())
|
|
|
-@@ -264,7 +324,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
- }
|
|
|
- --- a/arch/mips/ath79/irq.c
|
|
|
- +++ b/arch/mips/ath79/irq.c
|
|
|
--@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
|
|
|
-+@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(void)
|
|
|
- else if (soc_is_ar724x() ||
|
|
|
- soc_is_ar933x() ||
|
|
|
- soc_is_ar934x() ||
|
|
|
-@@ -272,19 +332,80 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
+@@ -272,16 +332,77 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
soc_is_qca955x())
|
|
|
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
|
|
|
else
|
|
@@ -317,40 +270,9 @@ index 5041619..403897a 100644
|
|
|
+ }
|
|
|
--- a/arch/mips/ath79/setup.c
|
|
|
+++ b/arch/mips/ath79/setup.c
|
|
|
--@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
|
|
|
-+@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type(void)
|
|
|
- u32 major;
|
|
|
- u32 minor;
|
|
|
- u32 rev = 0;
|
|
|
-@@ -292,7 +413,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
-
|
|
|
- id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
|
|
|
- major = id & REV_ID_MAJOR_MASK;
|
|
|
--@@ -151,6 +152,16 @@ static void __init ath79_detect_sys_type
|
|
|
-+@@ -152,6 +153,16 @@ static void __init ath79_detect_sys_type(void)
|
|
|
- rev = id & AR934X_REV_ID_REVISION_MASK;
|
|
|
- break;
|
|
|
-
|
|
|
-@@ -309,38 +430,60 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
- case REV_ID_MAJOR_QCA9556:
|
|
|
- ath79_soc = ATH79_SOC_QCA9556;
|
|
|
- chip = "9556";
|
|
|
--@@ -169,9 +180,9 @@ static void __init ath79_detect_sys_type
|
|
|
-+@@ -170,7 +181,7 @@ static void __init ath79_detect_sys_type(void)
|
|
|
-
|
|
|
- ath79_soc_rev = rev;
|
|
|
-
|
|
|
- - if (soc_is_qca955x())
|
|
|
--- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
|
|
|
--- chip, rev);
|
|
|
- + if (soc_is_qca953x() || soc_is_qca955x())
|
|
|
--+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
|
|
|
--+ chip, ver, rev);
|
|
|
-+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
|
|
|
-+ chip, rev);
|
|
|
- else
|
|
|
-- sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
|
|
|
-- pr_info("SoC: %s\n", ath79_sys_type);
|
|
|
+ @@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
|
|
|
+@@ -329,23 +450,49 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
+ pr_info("SoC: %s\n", ath79_sys_type);
|
|
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
|
-@@ -105,6 +105,9 @@
|
|
@@ -401,7 +323,7 @@ index 5041619..403897a 100644
|
|
|
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
|
|
|
+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
|
|
|
+
|
|
|
-@@ -351,7 +494,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
+@@ -356,7 +503,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
|
|
|
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
|
|
|
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
|
|
@@ -410,7 +332,7 @@ index 5041619..403897a 100644
|
|
|
+
|
|
|
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
|
|
|
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
|
|
|
-@@ -378,27 +521,85 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
+@@ -383,27 +530,85 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
|
|
|
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
|
|
|
#define QCA955X_PLL_CLK_CTRL_REG 0x08
|
|
@@ -500,7 +422,7 @@ index 5041619..403897a 100644
|
|
|
#define REV_ID_MAJOR_AR9341 0x0120
|
|
|
#define REV_ID_MAJOR_AR9342 0x1120
|
|
|
#define REV_ID_MAJOR_AR9344 0x2120
|
|
|
-@@ -407,7 +608,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
+@@ -412,7 +617,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
#define REV_ID_MAJOR_QCA9556 0x0130
|
|
|
#define REV_ID_MAJOR_QCA9558 0x1130
|
|
|
|
|
@@ -509,7 +431,7 @@ index 5041619..403897a 100644
|
|
|
|
|
|
#define AR934X_REV_ID_REVISION_MASK 0xf
|
|
|
|
|
|
-@@ -416,14 +617,81 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
+@@ -421,14 +626,81 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
|
|
#define QCA955X_REV_ID_REVISION_MASK 0xf
|
|
|
|
|
|
/*
|
|
@@ -594,7 +516,7 @@ index 5041619..403897a 100644
|
|
|
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
|
|
@@ -32,6 +32,7 @@ enum ath79_soc_type {
|
|
|
diff --git a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
|
|
|
-index 491a7aa..2bdc744 100644
|
|
|
+index ab2bc38..eecccdc 100644
|
|
|
--- a/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
|
|
|
+++ b/target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch
|
|
|
@@ -142,74 +142,9 @@
|
|
@@ -743,32 +665,8 @@ index 491a7aa..2bdc744 100644
|
|
|
else if (soc_is_qca955x())
|
|
|
qca955x_irq_init();
|
|
|
+ else if (soc_is_qca956x())
|
|
|
-@@ -519,7 +452,7 @@
|
|
|
- return -ENODEV;
|
|
|
- --- a/arch/mips/ath79/setup.c
|
|
|
- +++ b/arch/mips/ath79/setup.c
|
|
|
--@@ -175,15 +175,30 @@ static void __init ath79_detect_sys_type
|
|
|
-+@@ -175,14 +175,29 @@ static void __init ath79_detect_sys_type
|
|
|
- rev = id & QCA955X_REV_ID_REVISION_MASK;
|
|
|
- break;
|
|
|
-
|
|
|
-@@ -542,18 +475,18 @@
|
|
|
- ath79_soc_rev = rev;
|
|
|
-
|
|
|
- - if (soc_is_qca953x() || soc_is_qca955x())
|
|
|
-+- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
|
|
|
- + if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
|
|
|
-- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
|
|
|
-- chip, ver, rev);
|
|
|
-++ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
|
|
|
-++ chip, ver, rev);
|
|
|
- + else if (soc_is_tp9343())
|
|
|
- + sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
|
|
|
--+ chip, rev);
|
|
|
-+ chip, rev);
|
|
|
- else
|
|
|
- sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
|
|
|
-- pr_info("SoC: %s\n", ath79_sys_type);
|
|
|
+@@ -554,7 +487,7 @@
|
|
|
+ pr_info("SoC: %s\n", ath79_sys_type);
|
|
|
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
|
-@@ -131,6 +131,23 @@
|
|
@@ -776,7 +674,7 @@ index 491a7aa..2bdc744 100644
|
|
|
#define QCA955X_NFC_BASE 0x1b800200
|
|
|
#define QCA955X_NFC_SIZE 0xb8
|
|
|
|
|
|
-@@ -577,7 +510,7 @@
|
|
|
+@@ -578,7 +511,7 @@
|
|
|
#define AR9300_OTP_BASE 0x14000
|
|
|
#define AR9300_OTP_STATUS 0x15f18
|
|
|
#define AR9300_OTP_STATUS_TYPE 0x7
|
|
@@ -785,7 +683,7 @@ index 491a7aa..2bdc744 100644
|
|
|
#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
|
|
|
#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
|
|
|
|
|
|
-@@ -627,7 +560,7 @@
|
|
|
+@@ -628,7 +561,7 @@
|
|
|
/*
|
|
|
* USB_CONFIG block
|
|
|
*/
|
|
@@ -794,7 +692,7 @@ index 491a7aa..2bdc744 100644
|
|
|
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
|
|
|
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
|
|
|
|
|
|
-@@ -639,7 +572,7 @@
|
|
|
+@@ -640,7 +573,7 @@
|
|
|
#define MISC_INT_ETHSW BIT(12)
|
|
|
#define MISC_INT_TIMER4 BIT(10)
|
|
|
#define MISC_INT_TIMER3 BIT(9)
|
|
@@ -803,7 +701,7 @@ index 491a7aa..2bdc744 100644
|
|
|
|
|
|
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
|
|
|
|
|
-@@ -648,7 +581,7 @@
|
|
|
+@@ -649,7 +582,7 @@
|
|
|
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
|
|
#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
|
|
|
#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
|
|
@@ -812,7 +710,7 @@ index 491a7aa..2bdc744 100644
|
|
|
QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
|
|
|
QCA955X_EXT_INT_PCIE_RC2_INT3)
|
|
|
|
|
|
-@@ -686,7 +619,7 @@
|
|
|
+@@ -687,7 +620,7 @@
|
|
|
#define REV_ID_MAJOR_MASK 0xfff0
|
|
|
#define REV_ID_MAJOR_AR71XX 0x00a0
|
|
|
#define REV_ID_MAJOR_AR913X 0x00b0
|
|
@@ -821,7 +719,7 @@ index 491a7aa..2bdc744 100644
|
|
|
#define REV_ID_MAJOR_QCA9533_V2 0x0160
|
|
|
#define REV_ID_MAJOR_QCA9556 0x0130
|
|
|
#define REV_ID_MAJOR_QCA9558 0x1130
|
|
|
-@@ -695,7 +628,7 @@
|
|
|
+@@ -696,7 +629,7 @@
|
|
|
|
|
|
#define AR71XX_REV_ID_MINOR_MASK 0x3
|
|
|
#define AR71XX_REV_ID_MINOR_AR7130 0x0
|
|
@@ -830,7 +728,7 @@ index 491a7aa..2bdc744 100644
|
|
|
|
|
|
#define QCA955X_REV_ID_REVISION_MASK 0xf
|
|
|
|
|
|
-@@ -704,9 +637,9 @@
|
|
|
+@@ -705,9 +638,9 @@
|
|
|
/*
|
|
|
* SPI block
|
|
|
*/
|
|
@@ -843,7 +741,7 @@ index 491a7aa..2bdc744 100644
|
|
|
|
|
|
+#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
|
|
|
+#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
|
|
|
-@@ -724,9 +657,9 @@
|
|
|
+@@ -725,9 +658,9 @@
|
|
|
#define AR71XX_GPIO_COUNT 16
|
|
|
#define AR7240_GPIO_COUNT 18
|
|
|
#define AR7241_GPIO_COUNT 20
|