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@@ -0,0 +1,456 @@
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+From: Vincent Wiemann <me@bibbl.com>
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+Date: Sat, 6 Jan 2018 04:33:09 +0100
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+Subject: ramips: mtd: spi-nor: add support for switching between 3-byte and 4-byte addressing on w25q256 flash
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+
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+CAUTION! NEEDS TESTING!
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+Tries to backport switching between 3-byte and 4-byte addressing on w25q256 flash from Lede master (62ede4f78389c313a8004e79330a7d055eda2f7d) by Felix Fietkau.
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+
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+Applied patches:
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+mtd: spi-nor: rename SPINOR_OP_* macros of the 4-byte address op codes
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+mtd: spi-nor: add a stateless method to support memory size above 128Mib
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+mtd: spi-nor: add w25q256 3b-mode-switch
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+mtd: add chunked read-io to m25p80
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+
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+On some devices the flash chip needs to be in 3-byte addressing mode during
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+reboot, otherwise the boot loader will fail to start.
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+This mode however does not allow regular reads/writes onto the upper 16M
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+half. W25Q256 has separate read commands for reading from >16M, however
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+it does not have any separate write commands.
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+This patch changes the code to leave the chip in 3-byte mode most of the
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+time and only switch during erase/write cycles that go to >16M
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+addresses.
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+
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+Signed-off-by: Vincent Wiemann (me@bibbl.com)
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+
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+diff --git a/target/linux/ramips/patches-4.4/400-mtd-spi-nor-add-w25q256-3b-mode-switch.patch b/target/linux/ramips/patches-4.4/400-mtd-spi-nor-add-w25q256-3b-mode-switch.patch
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+new file mode 100644
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+index 0000000000000000000000000000000000000000..5399f547e4edd0eb1cfee8c1ec5b35e69c692ee9
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+--- /dev/null
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++++ b/target/linux/ramips/patches-4.4/400-mtd-spi-nor-add-w25q256-3b-mode-switch.patch
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+@@ -0,0 +1,399 @@
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++--- a/drivers/mtd/devices/serial_flash_cmds.h
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+++++ b/drivers/mtd/devices/serial_flash_cmds.h
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++@@ -18,19 +18,12 @@
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++ #define SPINOR_OP_RDVCR 0x85
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++
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++ /* JEDEC Standard - Serial Flash Discoverable Parmeters (SFDP) Commands */
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++-#define SPINOR_OP_READ_1_2_2 0xbb /* DUAL I/O READ */
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++-#define SPINOR_OP_READ_1_4_4 0xeb /* QUAD I/O READ */
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++-
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++ #define SPINOR_OP_WRITE 0x02 /* PAGE PROGRAM */
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++ #define SPINOR_OP_WRITE_1_1_2 0xa2 /* DUAL INPUT PROGRAM */
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++ #define SPINOR_OP_WRITE_1_2_2 0xd2 /* DUAL INPUT EXT PROGRAM */
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++ #define SPINOR_OP_WRITE_1_1_4 0x32 /* QUAD INPUT PROGRAM */
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++ #define SPINOR_OP_WRITE_1_4_4 0x12 /* QUAD INPUT EXT PROGRAM */
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++
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++-/* READ commands with 32-bit addressing */
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++-#define SPINOR_OP_READ4_1_2_2 0xbc
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++-#define SPINOR_OP_READ4_1_4_4 0xec
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++-
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++ /* Configuration flags */
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++ #define FLASH_FLAG_SINGLE 0x000000ff
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++ #define FLASH_FLAG_READ_WRITE 0x00000001
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++--- a/drivers/mtd/devices/st_spi_fsm.c
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+++++ b/drivers/mtd/devices/st_spi_fsm.c
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++@@ -507,13 +507,13 @@ static struct seq_rw_config n25q_read3_c
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++ * - 'FAST' variants configured for 8 dummy cycles (see note above.)
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++ */
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++ static struct seq_rw_config n25q_read4_configs[] = {
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++- {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 0, 8},
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++- {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
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++- {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 0, 8},
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++- {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
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++- {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
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++- {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
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++- {0x00, 0, 0, 0, 0, 0x00, 0, 0},
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+++ {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 0, 8},
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+++ {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
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+++ {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 0, 8},
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+++ {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
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+++ {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
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+++ {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
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+++ {0x00, 0, 0, 0, 0, 0x00, 0, 0},
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++ };
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++
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++ /*
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++@@ -553,13 +553,13 @@ static int stfsm_mx25_en_32bit_addr_seq(
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++ * entering a state that is incompatible with the SPIBoot Controller.
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++ */
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++ static struct seq_rw_config stfsm_s25fl_read4_configs[] = {
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++- {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ4_1_4_4, 0, 4, 4, 0x00, 2, 4},
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++- {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ4_1_1_4, 0, 1, 4, 0x00, 0, 8},
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++- {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ4_1_2_2, 0, 2, 2, 0x00, 4, 0},
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++- {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ4_1_1_2, 0, 1, 2, 0x00, 0, 8},
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++- {FLASH_FLAG_READ_FAST, SPINOR_OP_READ4_FAST, 0, 1, 1, 0x00, 0, 8},
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++- {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ4, 0, 1, 1, 0x00, 0, 0},
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++- {0x00, 0, 0, 0, 0, 0x00, 0, 0},
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+++ {FLASH_FLAG_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B, 0, 4, 4, 0x00, 2, 4},
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+++ {FLASH_FLAG_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B, 0, 1, 4, 0x00, 0, 8},
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+++ {FLASH_FLAG_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B, 0, 2, 2, 0x00, 4, 0},
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+++ {FLASH_FLAG_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B, 0, 1, 2, 0x00, 0, 8},
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+++ {FLASH_FLAG_READ_FAST, SPINOR_OP_READ_FAST_4B, 0, 1, 1, 0x00, 0, 8},
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+++ {FLASH_FLAG_READ_WRITE, SPINOR_OP_READ_4B, 0, 1, 1, 0x00, 0, 0},
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+++ {0x00, 0, 0, 0, 0, 0x00, 0, 0},
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++ };
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++
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++ static struct seq_rw_config stfsm_s25fl_write4_configs[] = {
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++--- a/drivers/mtd/spi-nor/spi-nor.c
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+++++ b/drivers/mtd/spi-nor/spi-nor.c
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++@@ -69,6 +69,14 @@ struct flash_info {
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++ #define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
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++ #define USE_FSR 0x80 /* use flag status register */
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++ #define SPI_NOR_HAS_LOCK 0x100 /* Flash supports lock/unlock via SR */
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+++#define SPI_NOR_4B_OPCODES 0x200 /*
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+++ * Use dedicated 4byte address op codes
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+++ * to support memory size above 128Mib.
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+++ */
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+++#define SPI_NOR_4B_READ_OP 0x400 /*
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+++ * Like SPI_NOR_4B_OPCODES, but for read
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+++ * op code only.
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+++ */
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++ };
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++
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++ #define JEDEC_MFR(info) ((info)->id[0])
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++@@ -182,6 +190,89 @@ static inline struct spi_nor *mtd_to_spi
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++ return mtd->priv;
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++ }
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++
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+++
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+++static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size)
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+++{
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+++ size_t i;
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+++
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+++ for (i = 0; i < size; i++)
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+++ if (table[i][0] == opcode)
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+++ return table[i][1];
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+++
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+++ /* No conversion found, keep input op code. */
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+++ return opcode;
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+++}
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+++
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+++static inline u8 spi_nor_convert_3to4_read(u8 opcode)
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+++{
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+++ static const u8 spi_nor_3to4_read[][2] = {
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+++ { SPINOR_OP_READ, SPINOR_OP_READ_4B },
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+++ { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B },
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+++ { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B },
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+++ { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
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+++ { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
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+++ { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
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+++ };
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+++
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+++ return spi_nor_convert_opcode(opcode, spi_nor_3to4_read,
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+++ ARRAY_SIZE(spi_nor_3to4_read));
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+++}
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+++
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+++static inline u8 spi_nor_convert_3to4_program(u8 opcode)
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+++{
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+++ static const u8 spi_nor_3to4_program[][2] = {
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+++ { SPINOR_OP_PP, SPINOR_OP_PP_4B },
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+++ { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
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+++ { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
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+++ };
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+++
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+++ return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
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+++ ARRAY_SIZE(spi_nor_3to4_program));
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+++}
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+++
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+++static inline u8 spi_nor_convert_3to4_erase(u8 opcode)
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+++{
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+++ static const u8 spi_nor_3to4_erase[][2] = {
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+++ { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B },
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+++ { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B },
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+++ { SPINOR_OP_SE, SPINOR_OP_SE_4B },
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+++ };
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+++
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+++ return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase,
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+++ ARRAY_SIZE(spi_nor_3to4_erase));
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+++}
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+++
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+++static void spi_nor_set_4byte_read(struct spi_nor *nor,
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+++ const struct flash_info *info)
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+++{
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+++ nor->addr_width = 3;
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+++ nor->ext_addr = 0;
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+++ nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
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+++ nor->flags |= SNOR_F_4B_EXT_ADDR;
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+++}
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+++
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+++
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+++
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+++static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
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+++ const struct flash_info *info)
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+++{
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+++ /* Do some manufacturer fixups first */
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+++ switch (JEDEC_MFR(info)) {
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+++ case SNOR_MFR_SPANSION:
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+++ /* No small sector erase for 4-byte command set */
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+++ nor->erase_opcode = SPINOR_OP_SE;
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+++ nor->mtd.erasesize = info->sector_size;
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+++ break;
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+++
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+++ default:
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+++ break;
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+++ }
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+++
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+++ nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode);
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+++ nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode);
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+++ nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode);
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+++}
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+++
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++ /* Enable/disable 4-byte addressing mode. */
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++ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
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++ int enable)
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++@@ -313,6 +404,36 @@ static void spi_nor_unlock_and_unprep(st
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++ mutex_unlock(&nor->lock);
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++ }
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++
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+++static int spi_nor_check_ext_addr(struct spi_nor *nor, u32 addr)
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+++{
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+++ bool ext_addr;
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+++ int ret;
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+++ u8 cmd;
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+++
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+++ if (!(nor->flags & SNOR_F_4B_EXT_ADDR))
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+++ return 0;
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+++
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+++ ext_addr = !!(addr & 0xff000000);
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+++ if (nor->ext_addr == ext_addr)
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+++ return 0;
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+++
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+++ cmd = ext_addr ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
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+++ write_enable(nor);
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+++ ret = nor->write_reg(nor, cmd, NULL, 0);
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+++ if (ret)
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+++ return ret;
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+++
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+++ cmd = 0;
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+++ ret = nor->write_reg(nor, SPINOR_OP_WREAR, &cmd, 1);
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+++ if (ret)
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+++ return ret;
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+++
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+++ nor->addr_width = 3 + ext_addr;
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+++ nor->ext_addr = ext_addr;
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+++ write_disable(nor);
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+++ return 0;
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+++}
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+++
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++ /*
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++ * Erase an address range on the nor chip. The address range may extend
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++ * one or more erase sectors. Return an error is there is a problem erasing.
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++@@ -338,6 +459,10 @@ static int spi_nor_erase(struct mtd_info
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++ if (ret)
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++ return ret;
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++
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+++ ret = spi_nor_check_ext_addr(nor, addr + len);
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+++ if (ret)
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+++ return ret;
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+++
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++ /* whole-chip erase? */
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++ if (len == mtd->size) {
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++ unsigned long timeout;
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++@@ -396,6 +521,7 @@ static int spi_nor_erase(struct mtd_info
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++ return ret;
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++
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++ erase_err:
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+++ spi_nor_check_ext_addr(nor, 0);
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++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
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++ instr->state = MTD_ERASE_FAILED;
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++ return ret;
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++@@ -585,7 +711,9 @@ static int spi_nor_lock(struct mtd_info
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++ if (ret)
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++ return ret;
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++
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+++ spi_nor_check_ext_addr(nor, ofs + len);
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++ ret = nor->flash_lock(nor, ofs, len);
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+++ spi_nor_check_ext_addr(nor, 0);
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++
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++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
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++ return ret;
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++@@ -600,7 +728,9 @@ static int spi_nor_unlock(struct mtd_inf
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++ if (ret)
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++ return ret;
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++
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+++ spi_nor_check_ext_addr(nor, ofs + len);
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++ ret = nor->flash_unlock(nor, ofs, len);
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+++ spi_nor_check_ext_addr(nor, 0);
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++
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++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
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++ return ret;
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++@@ -851,7 +981,7 @@ static const struct flash_info spi_nor_i
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++ { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
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++ { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
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++ { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
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++- { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
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+++ { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_READ_OP) },
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++
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++ /* Catalyst / On Semiconductor -- non-JEDEC */
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++ { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
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++@@ -898,8 +1028,23 @@ static int spi_nor_read(struct mtd_info
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++ if (ret)
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++ return ret;
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++
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+++ if (nor->flags & SNOR_F_4B_EXT_ADDR)
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+++ nor->addr_width = 4;
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+++
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++ ret = nor->read(nor, from, len, retlen, buf);
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++
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+++ if (nor->flags & SNOR_F_4B_EXT_ADDR) {
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+++ u8 val = 0;
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+++
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+++ if ((from + len) & 0xff000000) {
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+++ write_enable(nor);
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+++ nor->write_reg(nor, SPINOR_OP_WREAR, &val, 1);
|
|
|
+++ write_disable(nor);
|
|
|
+++ }
|
|
|
+++
|
|
|
+++ nor->addr_width = 3;
|
|
|
+++ }
|
|
|
+++
|
|
|
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
|
|
|
++ return ret;
|
|
|
++ }
|
|
|
++@@ -988,6 +1133,10 @@ static int spi_nor_write(struct mtd_info
|
|
|
++ if (ret)
|
|
|
++ return ret;
|
|
|
++
|
|
|
+++ ret = spi_nor_check_ext_addr(nor, to + len);
|
|
|
+++ if (ret < 0)
|
|
|
+++ return ret;
|
|
|
+++
|
|
|
++ write_enable(nor);
|
|
|
++
|
|
|
++ page_offset = to & (nor->page_size - 1);
|
|
|
++@@ -1018,6 +1167,7 @@ static int spi_nor_write(struct mtd_info
|
|
|
++
|
|
|
++ ret = spi_nor_wait_till_ready(nor);
|
|
|
++ write_err:
|
|
|
+++ spi_nor_check_ext_addr(nor, 0);
|
|
|
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
|
|
|
++ return ret;
|
|
|
++ }
|
|
|
++@@ -1366,27 +1516,12 @@ int spi_nor_scan(struct spi_nor *nor, co
|
|
|
++ else if (mtd->size > 0x1000000) {
|
|
|
++ /* enable 4-byte addressing if the device exceeds 16MiB */
|
|
|
++ nor->addr_width = 4;
|
|
|
++- if (JEDEC_MFR(info) == SNOR_MFR_SPANSION) {
|
|
|
++- /* Dedicated 4-byte command set */
|
|
|
++- switch (nor->flash_read) {
|
|
|
++- case SPI_NOR_QUAD:
|
|
|
++- nor->read_opcode = SPINOR_OP_READ4_1_1_4;
|
|
|
++- break;
|
|
|
++- case SPI_NOR_DUAL:
|
|
|
++- nor->read_opcode = SPINOR_OP_READ4_1_1_2;
|
|
|
++- break;
|
|
|
++- case SPI_NOR_FAST:
|
|
|
++- nor->read_opcode = SPINOR_OP_READ4_FAST;
|
|
|
++- break;
|
|
|
++- case SPI_NOR_NORMAL:
|
|
|
++- nor->read_opcode = SPINOR_OP_READ4;
|
|
|
++- break;
|
|
|
++- }
|
|
|
++- nor->program_opcode = SPINOR_OP_PP_4B;
|
|
|
++- /* No small sector erase for 4-byte command set */
|
|
|
++- nor->erase_opcode = SPINOR_OP_SE_4B;
|
|
|
++- mtd->erasesize = info->sector_size;
|
|
|
++- } else
|
|
|
+++ if (info->flags & SPI_NOR_4B_READ_OP)
|
|
|
+++ spi_nor_set_4byte_read(nor, info);
|
|
|
+++ else if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
|
|
|
+++ info->flags & SPI_NOR_4B_OPCODES)
|
|
|
+++ spi_nor_set_4byte_opcodes(nor, info);
|
|
|
+++ else
|
|
|
++ set_4byte(nor, info, 1);
|
|
|
++ } else {
|
|
|
++ nor->addr_width = 3;
|
|
|
++--- a/include/linux/mtd/spi-nor.h
|
|
|
+++++ b/include/linux/mtd/spi-nor.h
|
|
|
++@@ -42,9 +42,13 @@
|
|
|
++ #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
|
|
|
++ #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
|
|
|
++ #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
|
|
|
++-#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
|
|
|
++-#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
|
|
|
+++#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
|
|
|
+++#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
|
|
|
+++#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
|
|
|
+++#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
|
|
|
++ #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
|
|
|
+++#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
|
|
|
+++#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
|
|
|
++ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
|
|
|
++ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
|
|
|
++ #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
|
|
|
++@@ -55,11 +59,17 @@
|
|
|
++ #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
|
|
|
++
|
|
|
++ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
|
|
|
++-#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
|
|
|
++-#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
|
|
|
++-#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
|
|
|
++-#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
|
|
|
+++#define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
|
|
|
+++#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
|
|
|
+++#define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
|
|
|
+++#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
|
|
|
+++#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
|
|
|
+++#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
|
|
|
++ #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
|
|
|
+++#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
|
|
|
+++#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
|
|
|
+++#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
|
|
|
+++#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
|
|
|
++ #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
|
|
|
++
|
|
|
++ /* Used for SST flashes only. */
|
|
|
++@@ -70,6 +80,7 @@
|
|
|
++ /* Used for Macronix and Winbond flashes. */
|
|
|
++ #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
|
|
|
++ #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
|
|
|
+++#define SPINOR_OP_WREAR 0xc5 /* Write extended address register */
|
|
|
++
|
|
|
++ /* Used for Spansion flashes only. */
|
|
|
++ #define SPINOR_OP_BRWR 0x17 /* Bank register write */
|
|
|
++@@ -117,6 +128,7 @@ enum spi_nor_ops {
|
|
|
++ enum spi_nor_option_flags {
|
|
|
++ SNOR_F_USE_FSR = BIT(0),
|
|
|
++ SNOR_F_SST = BIT(1),
|
|
|
+++ SNOR_F_4B_EXT_ADDR = BIT(5),
|
|
|
++ };
|
|
|
++
|
|
|
++ /**
|
|
|
++@@ -166,6 +178,7 @@ struct spi_nor {
|
|
|
++ enum read_mode flash_read;
|
|
|
++ bool sst_write_second;
|
|
|
++ u32 flags;
|
|
|
+++ u8 ext_addr;
|
|
|
++ u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
|
|
|
++
|
|
|
++ int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
|
|
|
+diff --git a/target/linux/ramips/patches-4.4/401-mtd-add-chunked-read-io-to-m25p80.patch b/target/linux/ramips/patches-4.4/401-mtd-add-chunked-read-io-to-m25p80.patch
|
|
|
+new file mode 100644
|
|
|
+index 0000000000000000000000000000000000000000..b6111abad7063951c07688c66854fa743daeb6c6
|
|
|
+--- /dev/null
|
|
|
++++ b/target/linux/ramips/patches-4.4/401-mtd-add-chunked-read-io-to-m25p80.patch
|
|
|
+@@ -0,0 +1,21 @@
|
|
|
++--- a/drivers/mtd/spi-nor/spi-nor.c
|
|
|
+++++ b/drivers/mtd/spi-nor/spi-nor.c
|
|
|
++@@ -1176,6 +1176,7 @@ static int spi_nor_chunked_write(struct
|
|
|
++ size_t *_retlen, const u_char *_buf)
|
|
|
++ {
|
|
|
++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
|
|
|
+++ u32 addr_width = nor->addr_width + !!(nor->flags & SNOR_F_4B_EXT_ADDR);
|
|
|
++ int chunk_size;
|
|
|
++ int retlen = 0;
|
|
|
++ int ret;
|
|
|
++@@ -1184,8 +1185,8 @@ static int spi_nor_chunked_write(struct
|
|
|
++ if (!chunk_size)
|
|
|
++ chunk_size = _len;
|
|
|
++
|
|
|
++- if (nor->addr_width > 3)
|
|
|
++- chunk_size -= nor->addr_width - 3;
|
|
|
+++ if (addr_width > 3)
|
|
|
+++ chunk_size -= addr_width - 3;
|
|
|
++
|
|
|
++ while (retlen < _len) {
|
|
|
++ size_t len = min_t(int, chunk_size, _len - retlen);
|